# US 12,112,986 B2 · FinFET device and method

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- Number: US 12,112,986 B2
- Document ID: US12112986B2
- Status: Granted
- Kind: B2
- Application number: 17/382,562
- Filed: 2021-07-22
- Published: 2021-11-11
- Granted: 2024-10-08
- Earliest claimed: 2019-08-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Kun-Mu Li; Heng-Wen Ting; Hsueh-Chang Sung; Yen-Ru Lee; Chien-Wei Lee
- Web page: https://patentgrep.com/patent/US12112986B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/834: {comprising FinFETs}
- H10P 50/242: {of Group IV materials}
- H10P 50/693: {characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A device includes a fin over a substrate, the fin including a first end and a second end, wherein the first end of the fin has a convex profile, an isolation region adjacent the fin, a gate structure along sidewalls of the fin and over the top surface of the fin, a gate spacer laterally adjacent the gate structure, and an epitaxial region adjacent the first end of the fin.

## Claims

### Claim 1

A method of forming a semiconductor device, the method comprising:
forming a semiconductor structure over a substrate;
forming a dummy structure over the semiconductor structure;
forming a gate spacer on a sidewall of the dummy structure;
performing a first etching process on the semiconductor structure adjacent the dummy structure;
performing a second etching process on the semiconductor structure to form a reshaped semiconductor structure, wherein a first end of the reshaped semiconductor structure is a convex sidewall in a plan view when viewed from above the dummy structure; and
epitaxially growing a source/drain region adjacent ends of the reshaped semiconductor structure.

### Claim 2 (depends on 1)

The method of claim 1, wherein the semiconductor structure comprises a semiconductor fin, wherein forming the dummy structure comprises forming the dummy structure over an upper surface and sidewalls of the semiconductor fin.

### Claim 3 (depends on 1)

The method of claim 1, wherein the gate spacer is over the convex sidewall.

### Claim 4 (depends on 1)

The method of claim 1, wherein the source/drain region extends under the gate spacer.

### Claim 5 (depends on 1)

The method of claim 1, wherein the second etching process recesses the semiconductor structure under the gate spacer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the semiconductor structure after the second etching process is more convex than the semiconductor structure after the first etching process.

### Claim 7 (depends on 1)

The method of claim 1, wherein the first etching process is a first plasma etch process.

### Claim 8 (depends on 7)

The method of claim 7, wherein the second etching process is a second plasma etch process.

### Claim 9

A method of forming a semiconductor device, the method comprising:
forming a semiconductor strip over a substrate;
forming a dummy structure along sidewalls and a top surface of the semiconductor strip;
forming a gate spacer over the semiconductor strip adjacent the dummy structure;
removing a first portion of the semiconductor strip adjacent the dummy structure using a first etching process, wherein a sidewall of a first remaining portion of semiconductor strip has a first curvature after removing the first portion;
after removing the first portion, removing a second portion of the semiconductor strip adjacent the dummy structure using a second etching process, wherein a sidewall of a second remaining portion of semiconductor strip has a second curvature after removing the second portion, wherein the second curvature is greater than the first curvature; and
epitaxially growing a source/drain region adjacent the sidewall of the second remaining portion.

### Claim 10 (depends on 9)

The method of claim 9, further comprising forming an isolation region along a sidewall of the semiconductor strip, wherein an upper surface of the semiconductor strip is higher than an upper surface of the isolation region.

### Claim 11 (depends on 9)

The method of claim 9, wherein the source/drain region extends further under the gate spacer along a sidewall of the semiconductor strip than at a center region of the semiconductor strip in a plan view.

### Claim 12 (depends on 9)

The method of claim 9, wherein the sidewall of the first remaining portion is flat.

### Claim 13 (depends on 9)

The method of claim 9, wherein removing the second portion comprises performing a plasma etching process.

### Claim 14 (depends on 13)

The method of claim 13, wherein the plasma etching process uses H2, HCl, HBr, Cl2, CH4, C2H4, or SF6.

### Claim 15 (depends on 9)

The method of claim 9, wherein after removing the second portion a sidewall of the semiconductor strip is recessed from an edge of the gate spacer a distance in a range of 0.1 nm and 5 nm greater than a minimum distance from the semiconductor strip to the edge of the gate spacer in a plan view.

### Claim 16 (depends on 9)

The method of claim 9, wherein after removing the second portion a length of a sidewall of the semiconductor strip in a plan view is in a range of 9.5 nm and 40 nm, wherein after removing the second portion a length of the semiconductor strip along a center line in a plan view is in a range of 10 nm and 45 nm.

### Claim 17

A method of forming a semiconductor device, the method comprising:
forming a gate structure on a top surface of a semiconductor structure;
forming a gate spacer along sidewalls of the gate structure;
recessing the semiconductor structure adjacent the gate structure and the gate spacer to form a recess;
enlarging the recess, wherein after enlarging the recess a sidewall of a remaining portion of the semiconductor structure facing the recess has a convex curvature in a single plan view when viewed from above the gate structure; and
epitaxially growing a source/drain region adjacent the sidewall of the remaining portion.

### Claim 18 (depends on 17)

The method of claim 17, wherein the sidewall of the remaining portion of the semiconductor structure is laterally under the gate spacer.

### Claim 19 (depends on 17)

The method of claim 17, wherein enlarging the recess is performed at least in part by a plasma etching process.

### Claim 20 (depends on 17)

The method of claim 17, wherein the remaining portion of the semiconductor structure has a widest width in a middle region of the remaining portion.