# US 12,112,985 B2 · Semiconductor substrate

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- Number: US 12,112,985 B2
- Document ID: US12112985B2
- Status: Granted
- Kind: B2
- Application number: 18/520,518
- Filed: 2023-11-27
- Published: 2024-03-28
- Granted: 2024-10-08
- Earliest claimed: 2020-10-06
- Assignees: GlobalWafers Co., Ltd.
- Applicants: GlobalWafers Co., Ltd.
- Inventors: Chih-Yuan Chuang; Walter Tony Wohlmuth
- Web page: https://patentgrep.com/patent/US12112985B2

## CPC

- H10P 95/11: {Separation of active layers from substrates}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 62/82: Heterojunctions
- H10D 62/8325: {Silicon carbide}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10P 10/12: {Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates (preparing SOI wafers using bonding H10P90/1914)}
- H10P 14/3208: {Silicon carbide}
- H10P 14/3408: {Silicon carbide}
- H10P 14/3416: {Nitrides}
- H10P 54/52: {by cleaving}
- H10P 90/00: Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P 90/1916: {with separation or delamination along an ion implanted layer, e.g. Smart-cut}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10P 14/2926: {Crystal orientations}
- H10P 14/3211: {Silicon, silicon germanium or germanium}
- H10P 14/3248: {consisting of two layers}
- H10P 14/38: {characterised by treatments done after the formation of the materials}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10P 34/42: with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor substrate includes a high-resistivity silicon carbide layer and a gallium nitride epitaxial layer. The gallium nitride epitaxial layer is formed on a surface, a thickness of the gallium nitride epitaxial layer is less than 2 μm, and a full width at half maximum (FWHM) of an X-ray diffraction analysis (002) plane is less than 100 arcsec. The thickness of the high-resistivity silicon carbide layer ranges from 20 μm to 50 μm. The surface of the high-resistivity silicon carbide layer has an angle ranging from 0° to +/−8° with respect to a (0001) plane. The micropipe density (MPD) of the high-resistivity silicon carbide layer is less than 0.5 ea/cm2, the basal plane dislocation (BPD) of the high-resistivity silicon carbide layer is less than 10 ea/cm2, and the threading screw dislocation (TSD) of the high-resistivity silicon carbide layer is less than 500 ea/cm2.

## Claims

### Claim 1

A semiconductor substrate, comprising:
a high-resistivity silicon carbide layer comprising a first surface and a second surface opposite to the first surface; and
a gallium nitride epitaxial layer formed on the second surface of the high-resistivity silicon carbide layer, wherein a thickness of the gallium nitride epitaxial layer is less than 2 μm, and a full width at half maximum (FWHM) of an X-ray diffraction analysis (002) plane is less than 100 arcsec, and
a thickness of the high-resistivity silicon carbide layer ranges from 20 μm to 50 μm, the second surface of the high-resistivity silicon carbide layer has an angle ranging from 0° to +/−8° with respect to a (0001) plane, a micropipe density (MPD) of the high-resistivity silicon carbide layer is less than 0.5 ea/cm2, basal plane dislocation (BPD) of the high-resistivity silicon carbide layer is less than 10 ea/cm2, and threading screw dislocation (TSD) of the high-resistivity silicon carbide layer is less than 500 ea/cm2.

### Claim 2 (depends on 1)

The semiconductor substrate according to claim 1, wherein resistance of the high-resistivity silicon carbide layer is greater than 1E5 ohm-cm.

### Claim 3 (depends on 1)

The semiconductor substrate according to claim 1, wherein a resistance variation rate of the high-resistivity silicon carbide layer is less than 50%.

### Claim 4 (depends on 1)

The semiconductor substrate according to claim 1, further comprising a buffer layer, which is in direct contact with the first surface of the high-resistivity silicon carbide layer.

### Claim 5 (depends on 4)

The semiconductor substrate according to claim 4, wherein a thickness of the buffer layer is less than 1.5 μm.

### Claim 6 (depends on 1)

The semiconductor substrate according to claim 1, further comprising a laser lift off (LLO) layer, which is in direct contact with the first surface of the high-resistivity silicon carbide layer.

### Claim 7 (depends on 6)

The semiconductor substrate according to claim 6, wherein the laser lift off (LLO) layer is silicon carbide doped with aluminum.

### Claim 8 (depends on 6)

The semiconductor substrate according to claim 6, wherein a doping concentration of aluminum of the laser lift off (LLO) layer is greater than 1E20 cm−3, and a thickness of the laser lift off (LLO) layer ranges from 1.0 nm to 10 nm.

### Claim 9 (depends on 1)

The semiconductor substrate according to claim 1, further comprising a supporting substrate bonded to an exposed surface of the high-resistivity silicon carbide layer, wherein the supporting substrate comprises a silicon substrate, a silicon-on-insulator (SOI) substrate, a ceramic substrate, or a glass substrate.

### Claim 10

A semiconductor substrate, comprising:
an N-type silicon carbide (N—SiC) layer; and
a gallium nitride epitaxial layer formed on a surface of the N-type silicon carbide (N—SiC) layer, wherein a thickness of the gallium nitride epitaxial layer ranges from 0.3 μm to 6 μm, and a full width at half maximum (FWHM) of an X-ray diffraction analysis (002) plane is less than 100 arcsec, and
a thickness of the N-type silicon carbide (N—SiC) layer ranges from 0.1 μm to 50 μm, and the surface of the N-type silicon carbide (N—SiC) layer comprises an angle ranging from 0° to +/−8° with respect to a (0001) plane, a micropipe density (MPD) of the N-type silicon carbide (N—SiC) layer is less than 0.5 ea/cm2, basal plane dislocation (BPD) of the N-type silicon carbide (N—SiC) layer is less than 10 ea/cm2, and threading screw dislocation (TSD) of the N-type silicon carbide (N—SiC) layer is less than 500 ea/cm2.

### Claim 11 (depends on 10)

The semiconductor substrate according to claim 10, wherein resistance of the N-type silicon carbide (N—SiC) layer ranges from 1E15 cm−3 to 1E20 cm−3.

### Claim 12 (depends on 10)

The semiconductor substrate according to claim 10, wherein resistance variation rate of the N-type silicon carbide (N—SiC) layer is less than 5%.

### Claim 13 (depends on 10)

The semiconductor substrate according to claim 10, further comprising a supporting substrate bonded to an exposed surface of the N-type silicon carbide (N—SiC) layer, wherein the supporting substrate comprises a silicon substrate, a silicon-on-insulator (SOI) substrate, a ceramic substrate, or a glass substrate.