# US 12,112,981 B2 · Semiconductor device and method for fabricating semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,112,981 B2 - Document ID: US12112981B2 - Status: Granted - Kind: B2 - Application number: 17/679,133 - Filed: 2022-02-24 - Published: 2022-06-09 - Granted: 2024-10-08 - Earliest claimed: 2020-04-27 - Assignees: United Microelectronics Corp. - Applicants: United Microelectronics Corp. - Inventors: Zhi-Biao Zhou - Web page: https://patentgrep.com/patent/US12112981B2 ## CPC - H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)} - H10W 20/46: comprising air gaps - H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate - H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs} - H10W 20/072: {of dielectric parts comprising air gaps} - H10W 20/481: {on the rear surfaces of the wafers or substrates} - H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device is provided. The semiconductor device includes a device substrate, having a device structure layer and a buried dielectric layer, wherein the buried dielectric layer is disposed on a semiconductor layer of the device structure layer and the device substrate comprises a device structure. A metal layer is disposed on the buried dielectric layer and surrounded by a first inter-layer dielectric (ILD) layer. A region of the metal layer has a plurality of openings. The buried dielectric layer has an air gap under and exposing the region of the metal layer with the openings, wherein the air gap is located above the device structure in the device substrate. A second ILD layer is disposed on the metal layer and sealing the air gap at the openings of the metal layer. ## Claims ### Claim 1 A semiconductor device, comprising: a device substrate, having a device structure layer and a buried dielectric layer, wherein the buried dielectric layer is disposed on a semiconductor layer of the device structure layer and the device substrate comprises a device structure; a metal layer, disposed on the buried dielectric layer and surrounded by a first inter-layer dielectric (ILD) layer, wherein a region of the metal layer has a plurality of openings and the buried dielectric layer has an air gap under and exposing the region of the metal layer with the openings, wherein the air gap is located above the device structure in the device substrate; and a second ILD layer, disposed on the metal layer and sealing the air gap at the openings of the metal layer, wherein the device structure comprises a transistor device, and the air gap corresponds to a location of a channel of the transistor device. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the second ILD layer includes an interconnect structure embedded in the second ILD layer and electrically connecting to the metal layer. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, further comprising a through plug in the device substrate and the buried dielectric layer to connect between the metal layer and the device structure. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the openings of the metal layer are a plurality of parallel slits. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the openings of the metal layer are a plurality of holes arranged in an array distribution. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the first ILD layer surrounds the metal layer and covers a sidewall of the openings of the metal layer to reduce an aperture size of the openings. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein a sidewall of the openings of the metal layer remains not covered by the first ILD layer. ### Claim 8 (depends on 7) The semiconductor device of claim 7, further comprising a mask layer between the metal layer and the second ILD layer, wherein the mask layer has a plurality of openings, wherein each of the openings of the mask layer is located between and partially overlapping with adjacent two of the openings of the metal layer. ### Claim 9 (depends on 1) The semiconductor device of claim 1, wherein the air gap is located above the channel of the transistor device. ### Claim 10 (depends on 9) The semiconductor device of claim 9, wherein the transistor device is disposed on an SOI substrate. ### Claim 11 A method for fabricating a semiconductor device, comprising: providing a device substrate, having a device structure layer and a buried dielectric layer, wherein the buried dielectric layer is disposed on a semiconductor layer of the device structure layer and the device substrate comprises a device structure; forming a metal layer on the buried dielectric layer, wherein a first inter-layer dielectric (ILD) layer surrounds the metal layer, wherein a region of the metal layer has a plurality of openings; forming an air gap in the buried dielectric layer under and exposing the region of the metal layer with the openings, wherein the air gap is located above the device structure in the device substrate; and forming a second ILD layer on the metal layer and sealing the air gap at the openings of the metal layer, wherein the device structure comprises a transistor device, and the air gap corresponds to a location of a channel of the transistor device. ### Claim 12 (depends on 11) The method for fabricating the semiconductor device in claim 11, wherein the second ILD layer as formed includes an interconnection structure buried therein, electrically connecting to the metal layer. ### Claim 13 (depends on 12) The method for fabricating the semiconductor device in claim 12, further comprising forming a through plug in the device substrate and the buried dielectric layer to connect between the metal layer and the device structure. ### Claim 14 (depends on 11) The method for fabricating the semiconductor device in claim 11, wherein the openings of the metal layer are a plurality of parallel slits. ### Claim 15 (depends on 11) The method for fabricating the semiconductor device in claim 11, wherein the openings of the metal layer are a plurality of holes arranged in an array distribution. ### Claim 16 (depends on 11) The method for fabricating the semiconductor device in claim 11, wherein the first ILD layer surrounds the metal layer and covers a sidewall of the openings of the metal layer to reduce an aperture size of the openings. ### Claim 17 (depends on 11) The method for fabricating the semiconductor device in claim 11, wherein a sidewall of the openings of the metal layer remains not covered by the first ILD layer. ### Claim 18 (depends on 17) The method for fabricating the semiconductor device in claim 17, further comprising forming a mask layer between the metal layer and the second ILD layer, wherein the mask layer has a plurality of openings, wherein each of the openings of the mask layer is located between and partially overlapping with adjacent two of the openings of the metal layer. ### Claim 19 (depends on 11) The method for fabricating the semiconductor device in claim 11, wherein the air gap is located above the channel of the transistor device. ### Claim 20 (depends on 19) The method for fabricating the semiconductor device in claim 19, wherein the transistor device is disposed on an SOI substrate.