# US 12,112,980 B2 · Method to create air gaps

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- Number: US 12,112,980 B2
- Document ID: US12112980B2
- Status: Granted
- Kind: B2
- Application number: 17/304,697
- Filed: 2021-06-24
- Published: 2021-11-04
- Granted: 2024-10-08
- Earliest claimed: 2017-02-13
- Assignees: Lam Research Corporation
- Applicants: Lam Research Corporation
- Inventors: Patrick A. van Cleemput; Seshasayee Varadarajan; Bart J. van Schravendijk
- Web page: https://patentgrep.com/patent/US12112980B2

## CPC

- H10W 20/46: comprising air gaps
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/6939: {characterised by the metal}
- H10P 50/285: {of materials not containing Si, e.g. PZT or Al2O3}
- H10P 72/0421: {for drying etching}
- H10P 72/0606: {Position monitoring, e.g. misposition detection or presence detection}
- H10W 20/01: {Manufacture or treatment}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Tin oxide films are used to create air gaps during semiconductor substrate processing. Tin oxide films, disposed between exposed layers of other materials, such as SiO2 and SiN can be selectively etched using a plasma formed in an H2-containing process gas. The etching creates a recessed feature in place of the tin oxide between the surrounding materials. A third material, such as SiO2 is deposited over the resulting recessed feature without fully filling the recessed feature, forming an air gap. A method for selectively etching tin oxide in a presence of SiO2, SiC, SiN, SiOC, SiNO, SiCNO, or SiCN, includes, in some embodiments, contacting the substrate with a plasma formed in a process gas comprising at least about 50% H2. Etching of tin oxide can be performed without using an external bias at the substrate and is preferably performed at a temperature of less than about 100° C.

## Claims

### Claim 1

A method for creating an air gap on a semiconductor substrate, the method comprising:
(a) providing a semiconductor substrate having an exposed layer of a first material, an exposed layer of a second material, and an exposed layer of tin oxide positioned between the layer of the first material and the layer of the second material;
(b) selectively etching the exposed tin oxide relative to both the first and the second materials, and thereby forming a recessed feature between the first and second materials; and
(c) depositing a third material over the recessed feature without fully filling the recessed feature, and thereby forming the air gap between the layer of the first material and the layer of the second material.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first material is selected from the group consisting of SiO2, SiC, SiN, SiOC, SiNO, SiCNO, and SiCN, and wherein the second material is selected from the group consisting of SiO2, SiC, SiN, SiOC, SiNO, SiCNO, and SiCN.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first material and the second material are the same.

### Claim 4 (depends on 1)

The method of claim 1, wherein the third material is Sift.

### Claim 5 (depends on 1)

The method of claim 1, wherein (b) comprises exposing the semiconductor substrate to a plasma formed in a process gas comprising at least about 50% H2.

### Claim 6 (depends on 1)

The method of claim 1, wherein (b) comprises etching the exposed tin oxide using a hydrogen-containing plasma etch chemistry at a temperature of less than about 100° C.

### Claim 7 (depends on 1)

The method of claim 1, wherein the exposed layer of tin oxide residing between the layer of the first material and the layer of the second material has a width of between about 20-100 Å.

### Claim 8 (depends on 1)

The method of claim 1, further comprising, prior to (a):
forming a gate on the semiconductor substrate;
forming a layer of the first material over the semiconductor substrate, such that the first material covers both sidewalls and a top surface of the gate;
forming a tin oxide layer over the layer of the first material such that Tin oxide covers the first material both on the sidewalls and on the top surface of the gate;
forming a layer of the second material over the tin oxide layer, such that the second material covers the tin oxide both on the sidewalls and on the top surface of the gate; and
removing the second material from the horizontal surfaces of the substrate and thereby forming a structure provided in (a).

### Claim 9 (depends on 8)

The method of claim 8, wherein the first material is SiN and the second material is SiO2.

### Claim 10 (depends on 8)

The method of claim 8, wherein the gate comprises a high-k oxide.

### Claim 11 (depends on 8)

The method of claim 8, wherein the tin oxide is deposited to a thickness of between about 20-100 Å.

### Claim 12 (depends on 1)

The method of claim 1, further comprising:
applying photoresist to the semiconductor substrate;
exposing the photoresist to light;
patterning the photoresist and transferring the pattern to the substrate;
and selectively removing the photoresist from the substrate.