# US 12,112,978 B2 · Method for fabricating semiconductor device with redistribution plugs > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,112,978 B2 - Document ID: US12112978B2 - Status: Granted - Kind: B2 - Application number: 17/830,442 - Filed: 2022-06-02 - Published: 2023-12-07 - Granted: 2024-10-08 - Earliest claimed: 2022-06-02 - Assignees: Nanya Technology Corporation - Applicants: Nanya Technology Corporation - Inventors: Chun-Cheng Liao - Web page: https://patentgrep.com/patent/US12112978B2 ## CPC - H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning} - H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating} - H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 20/42: Vias, e.g. via plugs - H10W 20/425: {Barrier, adhesion or liner layers} - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10W 20/4405: {the principal metal being aluminium} - H10W 20/4421: {the principal metal being copper} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/611: {for connecting multiple chips together} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/652: Cross-sectional shapes - H10W 70/654: Top-view layouts - H10W 70/655: Fan-out layouts - H10W 70/685: comprising multiple insulating layers - H10W 72/01935: {by plating, e.g. electroless plating or electroplating} - H10W 72/01938: {in gaseous form, e.g. by CVD or PVD} - H10W 72/01951: {Changing the shapes of bond pads} - H10W 72/01953: {by etching} - H10W 72/90: Bond pads, in general - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/926: {Multiple bond pads having different sizes} - H10W 72/934: {Cross-sectional shape, i.e. in side view} - H10W 72/936: {Multiple bond pads having different shapes} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/9445: {Top-view layouts, e.g. mirror arrays} - H10W 80/312: {characterised by the direct bonding of electrically conductive pads} - H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers} - H10W 80/334: {Thermocompression bonding} - H10W 90/00: Package configurations - H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/792: {between multiple chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The present application discloses a method for fabricating a semiconductor device. The method includes providing a first chip comprising a first substrate, a first redistribution layer positioned above the first substrate, a first lower bonding pad positioned on the first redistribution layer, and a second lower bonding pad positioned above the first substrate and distant from the first lower bonding pad. The method also includes providing a second chip comprising a dense region and a loose region adjacent to the dense region; a plurality of upper pads positioned on the first lower bonding pad and the second lower bonding pad; and a plurality of second redistribution layers positioned on the plurality of upper pads. The method further performs bonding the second chip onto the first chip in a face-to-face manner, wherein the plurality of upper pads contact the first lower bonding pad and the second lower bonding pad. ## Claims ### Claim 1 A method for fabricating a semiconductor device, comprising: providing a first chip comprising a first substrate, a first redistribution layer positioned above the first substrate, a first lower bonding pad positioned on the first redistribution layer, and a second lower bonding pad positioned above the first substrate and distant from the first lower bonding pad; and providing a second chip comprising: a dense region and a loose region adjacent to the dense region; a plurality of upper pads positioned on the first lower bonding pad and the second lower bonding pad; a plurality of second redistribution layers positioned on the plurality of upper pads; and a first redistribution plug and a second redistribution plug respectively and correspondingly positioned on the plurality of second redistribution layers; bonding the second chip onto the first chip in a face-to-face manner to contact the plurality of upper pads to the first lower bonding pad and the second lower bonding pad; wherein the first redistribution plug is at the dense region and comprises a first aspect ratio; wherein the second redistribution plug is at the loose region and comprises a second aspect ratio less than the first aspect ratio. ### Claim 2 (depends on 1) The method of claim 1, further comprising: forming a plurality of lower pads on the first redistribution plug and the second redistribution plug; and forming a plug structure between the second lower bonding pad and the first substrate, wherein the plug structure is electrically coupled to the first redistribution plug. ### Claim 3 (depends on 2) The method of claim 2, wherein forming the plug structure comprises forming a bottom plug on the first substrate, forming a landing pad on the bottom plug, and forming a top plug between the landing pad and the second lower bonding pad. ### Claim 4 (depends on 3) The method of claim 3, wherein the bottom plug comprises aluminum, copper, or a combination thereof, and the top plug comprises tungsten. ### Claim 5 (depends on 4) The method of claim 4, wherein the second chip comprises a plurality of storage units above the first chip and electrically coupled to the first lower bonding pad or the second lower bonding pad, the plurality of storage units are configured as a capacitor array or a floating array, and the first chip is configured as a logic chip and the second chip is configured as a memory chip. ### Claim 6 (depends on 5) The method of claim 5, further comprising: forming a plurality of first supporting plugs respectively and correspondingly on the plurality of second redistribution layers, wherein the plurality of first supporting plugs are at the dense region and the loose region, respectively and correspondingly; and forming a plurality of second supporting plugs respectively and correspondingly on the plurality of second redistribution layers, wherein the plurality of second supporting plugs are at the dense region and the loose region, respectively and correspondingly. ### Claim 7 (depends on 6) The method of claim 6, wherein a distance between an adjacent pair of the first redistribution plug and the first supporting plug at the dense region and a distance between an adjacent pair of the first supporting plug and the second supporting plug at the dense region are substantially the same. ### Claim 8 (depends on 6) The method of claim 6, wherein a distance between an adjacent pair of the first redistribution plug and the first supporting plug at the dense region and a distance between an adjacent pair of the first supporting plug and the second supporting plug at the dense region are different. ### Claim 9 (depends on 6) The method of claim 6, wherein a distance between an adjacent pair of the second redistribution plug and the first supporting plug at the loose region and a distance between an adjacent pair of the first supporting plug and the second supporting plug at the loose region are substantially the same. ### Claim 10 (depends on 6) The method of claim 6, wherein a distance between an adjacent pair of the second redistribution plug and the first supporting plug at the loose region and a distance between an adjacent pair of the first supporting plug and the second supporting plug at the loose region are different. ### Claim 11 (depends on 6) The method of claim 6, wherein a distance between an adjacent pair of the first redistribution plug and the first supporting plug at the dense region and a distance between an adjacent pair of the second redistribution plug and the first supporting plug at the loose region are substantially the same. ### Claim 12 (depends on 6) The method of claim 6, wherein a distance between an adjacent pair of the first redistribution plug and the first supporting plug at the dense region and a distance between an adjacent pair of the second redistribution plug and the first supporting plug at the loose region are different. ### Claim 13 (depends on 6) The method of claim 6, wherein the plurality of first supporting plugs and the plurality of second supporting plugs are floating. ### Claim 14 A method for fabricating a semiconductor device, comprising: providing a first chip comprising a first substrate, a first redistribution layer above the first substrate, a first lower bonding pad on the first redistribution layer, a second lower bonding pad above the first substrate and distant from the first lower bonding pad, and a plug structure between the second lower bonding pad and the first substrate; and providing a second chip comprising: a dense region and a loose region adjacent to the dense region; a plurality of upper pads on the first lower bonding pad and the second lower bonding pad; a plurality of second redistribution layers on the plurality of upper pads; and a first redistribution plug and a second redistribution plug respectively and correspondingly on the plurality of second redistribution layers; bonding the second chip onto the first chip in a face-to-face manner to contact the plurality of bonding the second chip onto the first chip in a face-to-face manner to contact the plurality of upper pads to the first lower bonding pad and the second lower bonding pad; s to the first lower bonding pad and the second lower bonding pad; wherein the first redistribution plug is at the dense region, electrically couples to the first redistribution layer, and comprises a first aspect ratio; wherein the second redistribution plug is at the loose region, electrically couples to the plug structure, and comprises a second aspect ratio less than the first aspect ratio. ### Claim 15 (depends on 14) The method of claim 14, further comprising: forming a plurality of lower pads on the first redistribution plug and the second redistribution plug, wherein the plug structure comprises a bottom plug on the first substrate, a landing pad on the bottom plug, and a top plug between the landing pad and the second lower bonding pad. ### Claim 16 (depends on 15) The method of claim 15, wherein the bottom plug comprises aluminum, copper, or a combination thereof, and the top plug comprises tungsten. ### Claim 17 (depends on 16) The method of claim 16, wherein the second chip comprises a plurality of storage units above the first chip and electrically coupled to the first lower bonding pad or the second lower bonding pad. ### Claim 18 (depends on 17) The method of claim 17, wherein the plurality of storage units are configured as a capacitor array or a floating array. ### Claim 19 (depends on 18) The method of claim 18, wherein the first chip is configured as a logic chip and the second chip is configured as a memory chip. ### Claim 20 (depends on 19) The method of claim 19, further comprising: forming a plurality of first supporting plugs respectively and correspondingly on the plurality of second redistribution layers, wherein the plurality of first supporting plugs are at the dense region and the loose region, respectively and correspondingly; and forming a plurality of second supporting plugs respectively and correspondingly on the plurality of second redistribution layers, wherein the plurality of second supporting plugs are at the dense region and the loose region, respectively and correspondingly; wherein the plurality of first supporting plugs and the plurality of second supporting plugs are floating.