# US 12,112,974 B2 · Integrated circuit isolation feature and method of forming the same

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- Number: US 12,112,974 B2
- Document ID: US12112974B2
- Status: Granted
- Kind: B2
- Application number: 17/860,264
- Filed: 2022-07-08
- Published: 2022-10-27
- Granted: 2024-10-08
- Earliest claimed: 2018-09-25
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chih-Tang Peng; Shuen-Shin Liang; Keng-Chu Lin; Teng-Chun Tsai
- Web page: https://patentgrep.com/patent/US12112974B2

## CPC

- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/6322: {Formation by thermal treatments (formation by plasma treatment H10P14/6319)}
- H10P 14/6544: {to change the morphology of the insulating materials, e.g. transformation of an amorphous layer into a crystalline layer}
- H10P 14/6684: {the compound comprising silicon and oxygen}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 20/096: {by contacting with gases, liquids or plasmas}
- H10W 20/098: {by filling between adjacent conductive parts}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Examples of a technique for forming a dielectric material for an integrated circuit are provided herein. In an example, an integrated circuit workpiece is received that includes a recess. A first dielectric precursor is deposited in the recess. The first dielectric precursor includes a non-semiconductor component. A second dielectric precursor is deposited in the recess on the first dielectric precursor, and an annealing process is performed such that a portion of the non-semiconductor component of the first dielectric precursor diffuses into the second dielectric precursor. The non-semiconductor component may include oxygen, and the annealing process may be performed in one of a vacuum or an inert gas environment.

## Claims

### Claim 1

A method, comprising:
receiving a workpiece that includes a recess defined between two gate structures;
depositing a first dielectric precursor in the recess using flowable chemical vapor deposition (FCVD);
after the depositing of the first dielectric precursor, depositing a second dielectric precursor in the recess to directly contact top surfaces of the two gate structures, the second dielectric precursor comprising silicon and oxygen;
after the depositing of the second dielectric precursor, curing the second dielectric precursor using an ozone soak process;
after the curing of the second dielectric precursor, performing an annealing process such that oxygen in the first dielectric precursor diffuses into the second dielectric precursor to form a dielectric layer; and
after the annealing process, planarizing the workpiece to expose the top surfaces of the two gate structures,
wherein the depositing of the second dielectric precursor comprises depositing trisilylamine (TSA) using FCVD while supplying an oxygen-radical source, ammonia (NH3) or hydrogen (H2).

### Claim 2 (depends on 1)

The method of claim 1, wherein the two gate structures comprise polysilicon, and wherein the second dielectric precursor comprises silicon and nitrogen.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first dielectric precursor comprises a first ratio of oxygen to silicon, wherein the second dielectric precursor comprises a second ratio of oxygen to silicon, the second ratio being less than the first ratio.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
before the depositing of the second dielectric precursor, etching back the first dielectric precursor in the recess.

### Claim 5 (depends on 4)

The method of claim 4,
wherein the two gate structures comprise a gate height,
wherein the etching back terminates when a thickness of the first dielectric precursor is about one half of the gate height.

### Claim 6 (depends on 1)

The method of claim 1,
wherein the workpiece comprises a semiconductor fin including a source/drain feature exposed in the recess,
wherein the two gate structures are disposed over channel regions of the semiconductor fin, the channel regions being adjacent to the source/drain feature.

### Claim 7 (depends on 1)

The method of claim 1,
wherein the workpiece further comprises sidewall spacers disposed along sidewalls of the two gate structures,
wherein the first dielectric precursor and the dielectric layer are spaced apart from the two gate structures by the sidewall spacers.

### Claim 8 (depends on 1)

The method of claim 1, wherein the annealing process comprises a rapid thermal annealing.

### Claim 9 (depends on 1)

The method of claim 1, wherein the annealing process comprises an annealing temperature greater than 600° C.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
after the planarizing, replacing the two gate structures with two functional gate structures.

### Claim 11

A method, comprising:
providing a workpiece that includes:
a substrate,
a fin structure disposed on the substrate, the fin structure comprising a first channel region, a second channel region, and a source/drain region disposed between the first channel region and the second channel region,
a source/drain feature disposed over the source/drain region,
a first placeholder gate disposed over the first channel region, and
a second placeholder gate disposed over the second channel region;
forming a first dielectric precursor layer in a recess defined between the first placeholder gate and the second placeholder gate such that a top surface of the first dielectric precursor layer is lower than top surfaces of the first placeholder gate and the second placeholder gate;
after the forming of the first dielectric precursor layer, depositing a second dielectric precursor layer in the recess and over the first placeholder gate and the second placeholder gate, the second dielectric precursor layer comprising oxygen;
after the depositing of the second dielectric precursor layer, curing the second dielectric precursor layer using an ozone soak process; and
after the curing of the second dielectric precursor layer, performing an annealing process such that oxygen in the first dielectric precursor layer diffuses into the second dielectric precursor layer to form a dielectric layer,
wherein the forming of the second dielectric precursor layer comprises depositing trisilylamine (TSA) using flowable chemical vapor deposition (FCVD) while supplying an oxygen-radical source, ammonia (NH3) or hydrogen (H2).

### Claim 12 (depends on 11)

The method of claim 11, wherein the forming of the first dielectric precursor layer comprises:
depositing a first dielectric precursor using FCVD; and
etching back the deposited first dielectric precursor to form the first dielectric precursor layer,
wherein the etching back is performed such that a topmost surface of the first dielectric precursor layer is lower than a topmost surface of the first placeholder gate.

### Claim 13 (depends on 11)

The method of claim 11,
wherein the workpiece further comprises a first sidewall spacer disposed on a sidewall of the first placeholder gate and a second sidewall spacer disposed on a sidewall of the second placeholder gate.

### Claim 14 (depends on 13)

The method of claim 13,
wherein the first dielectric precursor layer is spaced apart from the first placeholder gate by the first sidewall spacer,
wherein the first dielectric precursor layer is spaced apart from the second placeholder gate by the second sidewall spacer.

### Claim 15 (depends on 13)

The method of claim 13,
wherein the first sidewall spacer and the second sidewall spacer comprise semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, or a semiconductor carbide.

### Claim 16 (depends on 11)

The method of claim 11, wherein the first dielectric precursor layer comprises a first ratio of oxygen to silicon, wherein the second dielectric precursor layer comprises a second ratio of oxygen to silicon, wherein the second ratio is less than the first ratio, wherein the second dielectric precursor layer further comprises nitrogen.

### Claim 17

A method, comprising:
providing a workpiece that includes:
a substrate,
an active region disposed on the substrate, the active region comprising a first channel region, a second channel region, and a source/drain region disposed between the first channel region and the second channel region,
a source/drain feature disposed over the source/drain region,
a first polysilicon gate disposed over the first channel region, and
a second polysilicon gate disposed over the second channel region;
forming a first dielectric precursor layer in a recess defined between the first polysilicon gate and the second polysilicon gate such that the first dielectric precursor layer is deposited on the source/drain feature;
curing the first dielectric precursor layer using a first annealing process;
after the curing of the first dielectric precursor layer, depositing a second dielectric precursor layer in the recess, over the first dielectric precursor layer and over a top surface of the first polysilicon gate and a top surface of the second polysilicon gate such that the second dielectric precursor layer is in direct contact with both the top surface of the first polysilicon gate and the top surface of the second polysilicon gate, the second dielectric precursor layer comprising oxygen;
after the depositing of the second dielectric precursor layer, curing the second dielectric precursor layer using a second annealing process;
after the curing of the second dielectric precursor layer, performing a third annealing process to form a dielectric layer from the first dielectric precursor layer and the second dielectric precursor layer; and
after the third annealing process, planarizing the workpiece such that top surfaces of the dielectric layer, the first polysilicon gate and the second polysilicon gate are coplanar,
wherein the depositing of the second dielectric precursor layer comprises depositing trisilylamine (TSA) using flowable chemical vapor deposition (FCVD) while supplying an oxygen-radical source, ammonia (NH3) or hydrogen (H2).

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
replacing the first polysilicon gate and the second polysilicon gate with a first functional gate and a second function gate, respectively.

### Claim 19 (depends on 17)

The method of claim 17, wherein the first dielectric precursor layer comprises a first ratio of oxygen to silicon, wherein the second dielectric precursor layer comprises a second ratio of oxygen to silicon, wherein the first ratio is greater than the second ratio.

### Claim 20 (depends on 17)

The method of claim 17, wherein the forming of the first dielectric precursor layer comprises:
depositing a first dielectric precursor over the recess using FCVD; and
etching back the deposited first dielectric precursor to form the first dielectric precursor layer,
wherein the etching back is performed such that a topmost surface of the first dielectric precursor layer is lower than a topmost surface of the first polysilicon gate.