# US 12,112,973 B2 · Semiconductor structure and method for manufacturing the same

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- Number: US 12,112,973 B2
- Document ID: US12112973B2
- Status: Granted
- Kind: B2
- Application number: 17/456,009
- Filed: 2021-11-22
- Published: 2022-04-28
- Granted: 2024-10-08
- Earliest claimed: 2020-10-23
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Tao Li
- Web page: https://patentgrep.com/patent/US12112973B2

## CPC

- H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 64/011: {of electrodes ohmically coupled to a semiconductor}
- H10D 64/01302: {the insulator being formed after the semiconductor body, the semiconductor being silicon}
- H10D 64/27: Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/66: Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D 64/68: characterised by the insulator, e.g. by the gate insulator
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10P 14/42: using a gas or vapour
- H10P 14/43: Chemical deposition, e.g. chemical vapour deposition [CVD]
- H10P 14/60: of insulating materials
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/6682: {the compound being a silane, e.g. disilane, methylsilane or chlorosilane}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The embodiment of the present invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises: a substrate having a trench therein; a first layer covering the bottom and the sidewall of the trench; and a second layer covering the surface of the first layer, wherein the step coverage of the second layer is different from the step coverage of the first layer. The embodiment of the invention is conducive to obtaining a multi-layer structure with preset step coverage.

## Claims

### Claim 1

A semiconductor structure, comprising:
a substrate of silicon, having a trench therein;
a first layer covering a bottom and a sidewall of the trench;
a second layer covering a surface of the first layer, wherein a step coverage of the second layer is different from a step coverage of the first layer; and,
wherein the first layer is formed by a low pressure chemical vapor deposition process, further comprises:
a gas pressure at the top of the trench greater than a gas pressure at the bottom of the trench; and
forming functional groups within the trench, and the functional groups serve to react with the substrate to generate preset material molecules, wherein a density of the functional groups at the bottom of the trench is lower than the density of the functional groups at a top of the trench; and
the sidewall of the trench comprises a bottom sidewall and a top sidewall, wherein the first layer covering the bottom sidewall is thinner than the first layer covering the top sidewall in a direction perpendicular to the sidewall of the trench.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the step coverage of the second layer is greater than the step coverage of the first layer.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein the second layer is a multi-layer structure, wherein at least two layers are of different materials.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein a thickness of the first layer decreases gradually from the top sidewall towards the bottom sidewall of the trench.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the first layer is of the same material as the second layer.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein the first layer and the second layer form a gate dielectric layer; and the semiconductor structure further comprises: a gate filled in the trench.

### Claim 7

A manufacturing method of a semiconductor structure, comprising:
providing a substrate of silicon having a trench therein;
forming a first layer covering a bottom and a sidewall of the trench;
forming a second layer covering a surface of the first layer, wherein a step coverage of the second layer is different from a step coverage of the first layer; and,
wherein the first layer is formed by a low pressure chemical vapor deposition process, further comprises:
a gas pressure at the top of the trench greater than a gas pressure at the bottom of the trench; and
forming functional groups within the trench, and the functional groups serve to react with the substrate to generate preset material molecules, wherein a density of the functional groups at the bottom of the trench is lower than the density of the functional groups at a top of the trench; and
the sidewall of the trench comprises a bottom sidewall and a top sidewall, wherein the first layer covering the bottom sidewall is thinner than the first layer covering the top sidewall in a direction perpendicular to the sidewall of the trench.

### Claim 8 (depends on 7)

The manufacturing method of claim 7, wherein the second layer is formed by atomic layer deposition process, wherein the step coverage of the second layer is greater than the step coverage of the first layer.

### Claim 9 (depends on 8)

The manufacturing method of claim 8, wherein the sidewall of the trench comprises a bottom sidewall and a top sidewall; the low pressure chemical vapor deposition process comprises: forming functional groups covering the sidewall of the trench which is used for immobilizing a first precursor, wherein the functional groups covering the bottom sidewall have a first density and the functional groups covering the top sidewall have a second density, with the second density being higher than the first density; and the first precursor and a second precursor are sequentially blown to the sidewall of the trench, wherein the second precursor is used to react with the immobilized first precursor to generate preset material molecules.

### Claim 10 (depends on 9)

The manufacturing method of claim 9, wherein an ambient pressure for forming the functional groups with the second density is 5 Torr to 10 Torr, and the ambient pressure for forming the functional groups with the first density is 0 Torr to 5 Torr.

### Claim 11 (depends on 7)

The manufacturing method of claim 7, wherein the first layer and the second layer constitute a gate dielectric layer; and after the formation of the second layer, the semiconductor structure further comprises: a gate filled in the trench.