# US 12,112,956 B2 · Chip interconnection package structure and method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,112,956 B2 - Document ID: US12112956B2 - Status: Granted - Kind: B2 - Application number: 17/434,480 - Filed: 2021-02-08 - Published: 2022-08-11 - Granted: 2024-10-08 - Earliest claimed: 2021-02-08 - Assignees: Institute of Semiconductors, Guangdong Academy of Sciences - Applicants: Institute of Semiconductors, Guangdong Academy of Sciences - Inventors: Yao Wang; Zibai Li; Yunzhi Ling; Xun Xiang; Yinhua Cui; Chuan Hu; Zhitao Chen - Web page: https://patentgrep.com/patent/US12112956B2 ## CPC - H10W 70/092: {Adapting interconnections, e.g. making engineering changes, repairing} - H10W 70/614: {the multiple chips being integrally enclosed} - H10P 72/74: {using temporarily an auxiliary support} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/095: {of vias therein} - H10W 70/611: {for connecting multiple chips together} - H10W 70/685: comprising multiple insulating layers - H10W 90/00: Package configurations - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10P 72/7422: {used to protect an active side of a device or wafer} - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/63: Vias, e.g. via plugs - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/9413: {on encapsulations} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)} - H10W 90/10: Configurations of laterally-adjacent chips - H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Provided are a chip interconnection package structure and method, including: forming a sacrificial pattern layer on a support structure; forming an interconnection winding pattern layer on the sacrificial pattern layer, wherein the interconnection winding pattern layer is corresponding to a sacrificial pattern of the sacrificial pattern layer in position; forming a first insulating layer on the interconnection winding pattern layer; forming a plurality of chips arranged at intervals on the first insulating layer, wherein the plurality of chips are respectively corresponding to the interconnection winding pattern of the interconnection winding pattern layer in position; and removing the support structure, and forming, on one side of the sacrificial pattern layer, a first interconnection hole penetrating through the sacrificial pattern, the interconnection winding pattern and the first insulating layer, and making the first interconnection hole aligned and communicated with a first interconnection pin of the chip corresponding in projection position. ## Claims ### Claim 1 A chip interconnection package method, wherein the method comprises: forming a sacrificial pattern layer on one side surface of a support structure; forming an interconnection winding pattern layer on the sacrificial pattern layer, wherein the interconnection winding pattern layer has an interconnection winding pattern which is corresponding to a sacrificial pattern of the sacrificial pattern layer in terms of position; forming a first insulating layer on the interconnection winding pattern layer; forming a plurality of chips arranged at intervals on the first insulating layer, wherein the plurality of chips are respectively corresponding to the interconnection winding pattern of the interconnection winding pattern layer in terms of position; and removing the support structure, and forming, on one side of the sacrificial pattern layer, a first interconnection hole penetrating through the sacrificial pattern, the interconnection winding pattern and the first insulating layer, wherein the first interconnection hole is aligned and communicated with a first interconnection pin of one chip of the plurality of chips which is corresponding in projection position. ### Claim 2 (depends on 1) The chip interconnection package method according to claim 1, wherein after the forming, on one side of the sacrificial pattern layer, a first interconnection hole penetrating through the sacrificial pattern, the interconnection winding pattern and the first insulating layer, wherein the first interconnection hole is aligned and communicated with a first interconnection pin of one chip of the plurality of chips which is corresponding in projection position, the method further comprises: forming a conductive material within the first interconnection hole, wherein the conductive material in the first interconnection hole is electrically connected to the interconnection winding pattern and the first interconnection pin of the chip. ### Claim 3 (depends on 2) The chip interconnection package method according to claim 2, wherein the interconnection winding pattern has a line width of 0.5 μm to 2 μm, and a line pitch of 0.5 μm to 2 μm. ### Claim 4 (depends on 2) The chip interconnection package method according to claim 2, wherein after the forming, on one side of the sacrificial pattern layer, a first interconnection hole penetrating through the sacrificial pattern, the interconnection winding pattern and the first insulating layer, wherein the first interconnection hole is aligned and communicated with a first interconnection pin of one chip of the plurality of chips which is corresponding in projection position, the method further comprises: removing the sacrificial pattern layer, or, removing a metal sacrificial layer when the sacrificial pattern layer comprises an insulating sacrificial layer and the metal sacrificial layer sequentially disposed on the interconnection winding pattern layer. ### Claim 5 (depends on 1) The chip interconnection package method according to claim 1, wherein the interconnection winding pattern has a line width of 0.5 μm to 2 μm, and a line pitch of 0.5 μm to 2 μm. ### Claim 6 (depends on 5) The chip interconnection package method according to claim 5, wherein after the forming, on one side of the sacrificial pattern layer, a first interconnection hole penetrating through the sacrificial pattern, the interconnection winding pattern and the first insulating layer, wherein the first interconnection hole is aligned and communicated with a first interconnection pin of one chip of the plurality of chips which is corresponding in projection position, the method further comprises: removing the sacrificial pattern layer, or, removing a metal sacrificial layer when the sacrificial pattern layer comprises an insulating sacrificial layer and the metal sacrificial layer sequentially disposed on the interconnection winding pattern layer. ### Claim 7 (depends on 1) The chip interconnection package method according to claim 1, wherein after the forming a plurality of chips arranged at intervals on the first insulating layer, the method further comprises: forming a plastic package on the plurality of chips. ### Claim 8 (depends on 7) The chip interconnection package method according to claim 7, wherein after the forming, on one side of the sacrificial pattern layer, a first interconnection hole penetrating through the sacrificial pattern, the interconnection winding pattern and the first insulating layer, wherein the first interconnection hole is aligned and communicated with a first interconnection pin of one chip of the plurality of chips which is corresponding in projection position, the method further comprises: removing the sacrificial pattern layer, or, removing a metal sacrificial layer when the sacrificial pattern layer comprises an insulating sacrificial layer and the metal sacrificial layer sequentially disposed on the interconnection winding pattern layer. ### Claim 9 (depends on 1) The chip interconnection package method according to claim 1, wherein after the forming, on one side of the sacrificial pattern layer, a first interconnection hole penetrating through the sacrificial pattern, the interconnection winding pattern and the first insulating layer, wherein the first interconnection hole is aligned and communicated with a first interconnection pin of one chip of the plurality of chips which is corresponding in projection position, the method further comprises: removing the sacrificial pattern layer, or, removing a metal sacrificial layer when the sacrificial pattern layer comprises an insulating sacrificial layer and the metal sacrificial layer sequentially disposed on the interconnection winding pattern layer. ### Claim 10 (depends on 9) The chip interconnection package method according to claim 9, wherein after the removing the sacrificial pattern layer, or, removing a metal sacrificial layer when the sacrificial pattern layer comprises an insulating sacrificial layer and a metal sacrificial layer sequentially disposed on the interconnection winding pattern layer, the method further comprises: forming a first package winding layer on one side of the interconnection winding pattern layer away from the chip; and forming, on one side of the first package winding layer, a second interconnection hole penetrating through the first package winding layer, wherein the second interconnection hole is aligned and communicated with the interconnection winding pattern corresponding in projection position. ### Claim 11 (depends on 10) The chip interconnection package method according to claim 10, wherein after forming a first package winding layer on one side of the interconnection winding pattern layer away from the chip, the method further comprises: forming, on one side of the first package winding layer, a third interconnection hole penetrating through the first package winding layer, wherein the third interconnection hole is aligned and communicated with a second interconnection pin of one chip of the plurality of chips corresponding in projection position. ### Claim 12 (depends on 11) The chip interconnection package method according to claim 11, wherein the forming a first package winding layer on one side of the interconnection winding pattern layer away from the chip comprises: forming a second insulating layer on one side of the interconnection winding pattern layer away from the chip; and forming a first package winding pattern layer on one side of the second insulating layer away from the chip, wherein a first package winding pattern of the first package winding pattern layer is corresponding to the interconnection winding pattern in terms of position. ### Claim 13 (depends on 11) The chip interconnection package method according to claim 11, wherein after the forming, on one side of the first package winding layer, a second interconnection hole penetrating through the first package winding layer, wherein the second interconnection hole is aligned and communicated with the interconnection winding pattern corresponding in projection position, the method further comprises: forming a second package winding layer on one side of the first package winding layer away from the chip; and forming, on one side of the second package winding layer, a fourth interconnection hole penetrating through the second package winding layer, wherein the fourth interconnection hole is aligned and communicated with the first package winding layer corresponding in projection position. ### Claim 14 (depends on 10) The chip interconnection package method according to claim 10, wherein the forming a first package winding layer on one side of the interconnection winding pattern layer away from the chip comprises: forming a second insulating layer on one side of the interconnection winding pattern layer away from the chip; and forming a first package winding pattern layer on one side of the second insulating layer away from the chip, wherein a first package winding pattern of the first package winding pattern layer is corresponding to the interconnection winding pattern in terms of position. ### Claim 15 (depends on 14) The chip interconnection package method according to claim 14, wherein after the forming, on one side of the first package winding layer, a second interconnection hole penetrating through the first package winding layer, wherein the second interconnection hole is aligned and communicated with the interconnection winding pattern corresponding in projection position, the method further comprises: forming a second package winding layer on one side of the first package winding layer away from the chip; and forming, on one side of the second package winding layer, a fourth interconnection hole penetrating through the second package winding layer, wherein the fourth interconnection hole is aligned and communicated with the first package winding layer corresponding in projection position. ### Claim 16 (depends on 15) The chip interconnection package method according to claim 15, wherein the forming a second package winding layer on one side of the first package winding layer away from the chip comprises: forming a third insulating layer on one side of the first package winding layer away from the chip; and forming a second package winding pattern layer on one side of the third insulating layer away from the chip. ### Claim 17 (depends on 16) The chip interconnection package method according to claim 16, wherein a line width of a second package winding pattern of the second package winding pattern layer is greater than 5 μm. ### Claim 18 (depends on 15) The chip interconnection package method according to claim 15, wherein a line width of the first package winding pattern of the first package winding pattern layer is 2 μm to 5 μm, and a line pitch of the first package winding pattern of the first package winding pattern layer is 2 μm to 5 μm. ### Claim 19 (depends on 14) The chip interconnection package method according to claim 14, wherein a line width of the interconnection winding pattern is smaller than a line width of the first package winding pattern of the first package winding pattern layer; and a line pitch of the interconnection winding pattern is smaller than a line pitch of the first package winding pattern of the first package winding pattern layer. ### Claim 20 (depends on 1) A chip interconnection package structure, wherein the chip interconnection package structure is prepared by adopting the chip interconnection package method according to claim 1, comprising: sequentially providing the interconnection winding pattern layer and the plurality of chips on the sacrificial pattern layer, wherein the winding pattern of the interconnection winding pattern layer is corresponding to the sacrificial pattern of the sacrificial pattern layer in terms of position, and the plurality of chips are respectively arranged correspondingly on the interconnection winding pattern of the interconnection winding pattern layer; and forming, on one side of the sacrificial pattern layer, the first interconnection hole penetrating through the sacrificial pattern and the interconnection winding pattern, wherein the first interconnection hole is aligned and communicated with the first interconnection pin of one of the plurality of chips corresponding in projection position.