# US 12,112,951 B2 · Integrated dipole region for transistor

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- Number: US 12,112,951 B2
- Document ID: US12112951B2
- Status: Granted
- Kind: B2
- Application number: 17/673,905
- Filed: 2022-02-17
- Published: 2023-08-17
- Granted: 2024-10-08
- Earliest claimed: 2022-02-17
- Assignees: Applied Materials, Inc.
- Applicants: Applied Materials, Inc.
- Inventors: Srinivas Gandikota; Yixiong Yang; Steven C. H. Hung; Tianyi Huang; Seshadri Ganguli
- Web page: https://patentgrep.com/patent/US12112951B2

## CPC

- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/0134: {with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which comprise an integrated dipole region to meet reduced thickness and lower thermal budget requirements. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, and a dipole region having an interfacial layer, a metal film substantially free of non-metal atoms on the interfacial layer, and a high-κ dielectric layer on the metal film. In some embodiments, the dipole region of the electronic devices comprises an interfacial layer, a high-κ dielectric layer on the interfacial layer, and a metal film on the high-κ dielectric layer. In some embodiments, the methods comprise annealing the substrate to drive particles of metal from the metal film into one or more of the interfacial layer or the high-κ dielectric layer.

## Claims

### Claim 1

A method of manufacturing an electronic device, the method comprising:
depositing an interfacial layer on a top surface of a channel located between a source and a drain on a substrate;
depositing a metal film on the interfacial layer, the metal film comprising titanium aluminum (TiAl); and
depositing a high-κ dielectric layer on the metal film to form a dipole region.

### Claim 2 (depends on 1)

The method of claim 1, wherein the interfacial layer comprises a dielectric material.

### Claim 3 (depends on 2)

The method of claim 2, wherein the dielectric material is selected from one or more of silicon (Si), silicon dioxide (SiO2), doped silicon, doped silicon oxide, or spin-on dielectrics.

### Claim 4 (depends on 1)

The method of claim 1, wherein the channel comprises n-type material and the metal film comprises one or more of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), magnesium (Mg), scandium (Sc), strontium (Sr), yttrium (Y), zirconium (Zr), or caesium (Cs).

### Claim 5 (depends on 1)

The method of claim 1, wherein the channel comprises p-type material and the metal film comprises one or more of aluminum (Al), titanium (Ti), gallium (Ga), germanium (Ge), selenium (Se), indium (In), tin (Sn), antimony (Sb), tellurium (Te), tantalum (Ta), tungsten (W), or molybdenum (Mo).

### Claim 6 (depends on 1)

The method of claim 1, wherein the high-κ dielectric layer comprises one or more of hafnium oxide (HfOx), zirconium oxide (ZrOx), or hafnium zirconium (HfZr).

### Claim 7 (depends on 1)

The method of claim 1, wherein the electronic device comprises alternating layers of metal film and high-κ dielectric layer.

### Claim 8 (depends on 1)

The method of claim 1, further comprising annealing the substrate at a temperature in a range of 400° C. to 900° C. to drive particles of metal from the metal film into the high-κ dielectric layer.

### Claim 9 (depends on 1)

The method of claim 1, further comprising depositing a capping layer on the dipole region, the capping layer comprising one or more of titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), silicon (Si), or titanium aluminum (TiAl).