# US 12,112,950 B2 · Semiconductor device with protection layer and method for fabricating the same

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- Number: US 12,112,950 B2
- Document ID: US12112950B2
- Status: Granted
- Kind: B2
- Application number: 17/667,667
- Filed: 2022-02-09
- Published: 2023-08-10
- Granted: 2024-10-08
- Earliest claimed: 2022-02-09
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Ming-Hung Hsieh
- Web page: https://patentgrep.com/patent/US12112950B2

## CPC

- H10B 12/50: {Peripheral circuit region structures}
- H10D 64/01312: {the additional layer comprising a metal or metal silicide formed by deposition, i.e. without a silicidation reaction, e.g. sputter deposition}
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/488: {Word lines}
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/43: Chemical deposition, e.g. chemical vapour deposition [CVD]
- G11C 8/14: Word line organisation; Word line lay-out
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; and a first gate stack positioned on the substrate and including: a first gate dielectric layer positioned on the substrate; a first gate protection layer positioned on the first gate dielectric layer and including titanium silicon nitride; a first work function layer positioned on the first gate protection layer; and a first gate filler layer positioned on the first work function layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a first gate stack positioned on the substrate and comprising:
a first gate dielectric layer positioned on the substrate;
a first gate protection layer positioned on the first gate dielectric layer and comprising titanium silicon nitride;
a first work function layer positioned on the first gate protection layer;
a first gate filler layer positioned on the first work function layer, wherein a thickness of the first gate filler layer is larger than a thickness of the first gate dielectric layer;
a first gate barrier layer positioned between the first work function layer and the first gate filler layer, wherein a bottom side of the first gate barrier layer is in direct contact with a top side of the first work function layer while a top side of the first gate barrier layer is in direct contact with a bottom side of the first gate filler layer;
a first gate capping layer positioned on the first gate filler layer, wherein a bottom side of the first gate capping layer is in contact with a top side of the first gate filler layer, wherein a thickness of the first gate capping layer is smaller than the thickness of the first gate filler layer; and
a first spacer layer disposed on two sidewalls of the first gate stack, wherein a bottom side of the first spacer layer is in contact with a top side of the substrate and a top end of the first spacer layer is coplanar with a top side of the first gate capping layer, wherein a width of the top end of the first spacer layer is smaller than a width of the bottom side of the first spacer layer;
an interfacial layer which has a bottom side in contact with the top side of the substrate and a top side in contact with the first gate dielectric layer, wherein the interfacial layer is formed of a chemical oxide of the substrate, wherein the substrate comprises an array area and a peripheral area surrounding the array area, and the first gate stack is positioned on the peripheral area of the first gate dielectric layer; and
an adjustment layer which has a bottom side in contact with the first gate protection layer and a top side in contact with the first work function layer for fine-tuning a threshold voltage of the first gate stack, wherein the first gate barrier layer comprises titanium nitride, or titanium/titanium nitride bi-layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising a dipole layer which has a bottom side in contact with a top side of the interfacial layer and a top side in contact with a bottom side of the first gate dielectric layer, wherein the first gate capping layer comprises silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or fluoride-doped silicate, wherein the first gate capping layer and the first spacer layer are made of a same material.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, further comprising an isolation layer positioned in the peripheral area of the substrate and defining a first active area and a second active area next to the first active area;
wherein the first gate stack is positioned on the first active area;
wherein the first work function layer comprises a bottom work function layer positioned on the first gate protection layer and a top work function layer positioned on the bottom work function layer, wherein the bottom side of the first gate barrier layer is in direct contact with the top work function layer, wherein the bottom work function layer and the top work function layer are made of different materials.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, further comprising:
a functional layer which has a bottom side in contact with a top side of the first gate dielectric layer and a top side in contact with a bottom side of the first gate protection layer; and
a plurality of first impurity regions positioned in the first active area and adjacent to the first gate dielectric layer, wherein the first gate stack is contactless with the first impurity regions while the first spacer layer is disposed on and is in direct contact with at least one of the first impurity regions.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, further comprising a second gate stack positioned on the second active area and comprising:
a second gate dielectric layer positioned on the second active area;
a second gate protection layer positioned on the second gate dielectric layer and comprising titanium silicon nitride;
a second work function layer positioned on the second gate protection layer;
a second gate filler layer positioned on the second work function layer;
a second gate barrier layer positioned between the second work function layer and the second gate filler layer, wherein a bottom side of the second gate barrier layer is in direct contact with a top side of the second work function layer while a top side of the second gate barrier layer is in direct contact with a bottom side of the second gate filler layer;
a second gate capping layer positioned on the second gate filler layer, wherein a bottom side of the second gate capping layer is in contact with a top side of the second gate filler layer, wherein a thickness of the second gate capping layer is smaller than a thickness of the second gate filler layer; and
a second spacer layer disposed on two sidewalls of the second gate stack, wherein a bottom side of the second spacer layer is in contact with a top side of the substrate and a top end of the second spacer layer is coplanar with a top side of the second gate capping layer, wherein a width of the top end of the second spacer layer is smaller than a width of the bottom side of the second spacer layer.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the thickness of the first gate dielectric layer and a thickness of the second gate dielectric layer are substantially the same, wherein the thickness of each of the first gate dielectric layer and the second gate dielectric layer is between 0.5 nm and 5.0 nm, wherein the thickness of the first gate filler layer and the thickness of the second gate filler layer are the same.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the first work function layer and the second work function layer comprise aluminum, silver, titanium, titanium nitride, titanium aluminum, titanium carbide aluminum, titanium nitride aluminum, titanium silicon aluminum, tantalum nitride, tantalum carbide, tantalum silicon nitride, manganese, zirconium, or tungsten nitride, wherein a thickness of each of the first work function layer and the second work function layer is between 10 angstroms and 200 angstroms, wherein the thickness of the second gate filler layer is larger than the thickness of the second gate dielectric layer.

### Claim 8 (depends on 6)

The semiconductor device of claim 6, wherein the first work function layer and the second work function layer comprise different materials.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, further comprising a plurality of second impurity regions positioned in the second active area and adjacent to the second gate dielectric layer, wherein the second gate stack is contactless with the second impurity regions while the second spacer layer is disposed on and is in direct contact with at least one of the second impurity regions, wherein the second gate capping layer and the second spacer layer are made of a same material.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein an electrical type of the plurality of first impurity regions and an electrical type of the plurality of second impurity regions are the same.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein an electrical type of the plurality of first impurity regions and an electrical type of the plurality of second impurity regions are different.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, further comprising a word line structure positioned in the array area, wherein the isolation layer further defines an array active area in the array area, wherein the word line structure is positioned in the array active area of the array area.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the word line structure comprises:
a word line insulating layer inwardly positioned in the array area, wherein the word line insulating layer has a U-shaped configuration;
a word line barrier layer having a U-shaped configuration disposed in the word line insulating layer at a position that a top side of the word line barrier layer is coplanar with a top side of the word line insulating layer;
a word line conductive layer disposed in the word line barrier layer at a position that a top side of the word line conductive layer is coplanar with the top side of the word line insulting layer and the top side of the word line barrier layer; and
a word line capping layer positioned on the word line insulating layer and the word line conductive layer at a position that a bottom side of the word line capping layer is direct contact with the top sides of the word line conductive layer, the word line barrier layer, and the word line insulting layer.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the word line capping layer comprises a bottom portion positioned on the word line insulating layer, the word line barrier layer, and the word line conductive layer, and a top portion positioned on and in direct contact with the bottom portion;
wherein a width of the word line capping layer is equal to a width of the word line insulating layer;
wherein the bottom portion comprises an insulating material having a dielectric constant of about 4.0 or greater;
wherein the top portion comprises a low dielectric-constant material.