# US 12,112,942 B2 · Deposition process for forming semiconductor device and system

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- Number: US 12,112,942 B2
- Document ID: US12112942B2
- Status: Granted
- Kind: B2
- Application number: 17/818,823
- Filed: 2022-08-10
- Published: 2022-12-01
- Granted: 2024-10-08
- Earliest claimed: 2019-12-24
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chung-Ting Ko; Chi On Chui
- Web page: https://patentgrep.com/patent/US12112942B2

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- C23C 16/45525: {Atomic layer deposition [ALD]}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/6682: {the compound being a silane, e.g. disilane, methylsilane or chlorosilane}
- H10P 14/69391: {the material containing aluminium, e.g. Al2O3}
- H10P 14/69392: {the material containing hafnium, e.g. HfO2}
- H10P 14/69395: {the material containing zirconium, e.g. ZrO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/098: {by filling between adjacent conductive parts}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/011: {of electrodes ohmically coupled to a semiconductor}
- H10P 32/12: between a solid phase and a gaseous phase
- H10P 32/17: {characterised by the semiconductor material}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes placing a semiconductor substrate in a deposition chamber, wherein the semiconductor substrate includes a trench, and performing an atomic layer deposition (ALD) process to deposit a dielectric material within the trench, including flowing a first precursor of the dielectric material into the deposition chamber as a gas phase; flowing a second precursor of the dielectric material into the deposition chamber as a gas phase; and controlling the pressure and temperature within the deposition chamber such that the second precursor condenses on surfaces within the trench as a liquid phase of the second precursor, wherein the liquid phase of the second precursor has capillarity.

## Claims

### Claim 1

A method comprising:
forming a fin protruding from a semiconductor substrate;
forming a gate stack over and along sidewalls of the fin;
forming an isolation region over the fin and surrounding the gate stack; and
depositing a dielectric material on the gate stack, comprising flowing a plurality of gaseous precursors over the gate stack, wherein at least one gaseous precursor of the plurality of gaseous precursors condenses on surfaces as a liquid having capillarity.

### Claim 2 (depends on 1)

The method of claim 1 further comprising recessing a top surface of the gate stack before depositing the dielectric material.

### Claim 3 (depends on 1)

The method of claim 1, wherein the dielectric material is free of seams.

### Claim 4 (depends on 1)

The method of claim 1, wherein the at least one gaseous precursor comprises water.

### Claim 5 (depends on 1)

The method of claim 1, wherein the dielectric material comprises aluminum oxide.

### Claim 6 (depends on 1)

The method of claim 1, wherein the liquid condenses into a thicker layer on bottom surfaces than on sidewall surfaces.

### Claim 7 (depends on 1)

The method of claim 1, wherein the dielectric material is deposited over the isolation region.

### Claim 8 (depends on 1)

The method of claim 1, wherein the dielectric material is deposited using an Atomic Layer Deposition (ALD) process.

### Claim 9

A method comprising:
forming a plurality of semiconductor fins on a substrate;
forming a gate structure extending over the plurality of semiconductor fins;
forming spacers on sidewalls of the gate structure;
performing an etching process to recess the gate structure and the spacers; and
performing a deposition process to form a hard mask material on the gate structure and the spacers, wherein the deposition process comprises:
introducing a first precursor into a process chamber as a gas, wherein the first precursor remains a gas during the deposition process; and
introducing a second precursor into the process chamber as a gas, wherein the second precursor condenses into a liquid during the deposition process.

### Claim 10 (depends on 9)

The method of claim 9, wherein a vertical deposition rate of the hard mask material is greater than a lateral deposition rate of the hard mask material.

### Claim 11 (depends on 9)

The method of claim 9, wherein the liquid has capillarity.

### Claim 12 (depends on 9)

The method of claim 9 further comprising forming a contact penetrating the hard mask material to contact the gate structure.

### Claim 13 (depends on 9)

The method of claim 9, wherein the hard mask material comprises silicon nitride.

### Claim 14 (depends on 9)

The method of claim 9, wherein the second precursor comprises ammonia.

### Claim 15 (depends on 9)

The method of claim 9, wherein the first precursor comprises trimethylaluminum (TMA).

### Claim 16 (depends on 9)

The method of claim 9, wherein the deposition process comprises a process pressure in the range of 0.5 Torr to 50 Torr and a process temperature in the range of 30° C. to 300° C.

### Claim 17

A method comprising:
forming a fin protruding from a substrate;
forming an isolation region surrounding the fin;
forming a gate stack over the fin;
forming a source/drain region in the fin adjacent the gate stack;
forming an inter-layer dielectric (ILD) over the source/drain region, wherein a top surface of the gate stack is recessed from a top surface of the ILD;
forming a hard mask covering the gate stack, wherein a top surface of the hard mask is level with the top surface of the ILD, wherein the hard mask is free of seams, wherein the hard mask has a height:width aspect ratio in the range between 1:3 and 1:25; and wherein the hard mask comprises a metal oxide; and
forming a conductive feature extending through the hard mask to contact the gate stack.

### Claim 18 (depends on 17)

The method of claim 17, wherein the metal oxide is aluminum oxide, zirconium oxide, or hafnium oxide.

### Claim 19 (depends on 17)

The method of claim 17 further comprising forming gate spacers along sidewalls of the gate stack, wherein the hard mask covers the gate spacers.

### Claim 20 (depends on 17)

The method of claim 17, wherein the hard mask has a smallest width in the range between 3 nm and 10 nm.