# US 12,112,893 B2 · Ceramic electronic device and manufacturing method of the same

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- Number: US 12,112,893 B2
- Document ID: US12112893B2
- Status: Granted
- Kind: B2
- Application number: 17/860,946
- Filed: 2022-07-08
- Published: 2023-02-09
- Granted: 2024-10-08
- Earliest claimed: 2021-07-28
- Assignees: Taiyo Yuden Co., Ltd.
- Applicants: Taiyo Yuden Co., Ltd.
- Inventors: Tomoaki Nakamura; Mikio Tahara
- Web page: https://patentgrep.com/patent/US12112893B2

## CPC

- H01G 4/2325: {characterised by the material of the terminals}
- H01G 4/248: the terminals embracing or surrounding the capacitive element, e.g. caps (H01G4/252 takes precedence)
- H01G 4/30: Stacked capacitors (H01G4/33 takes precedence)
- H01G 4/12: Ceramic dielectrics {(H01G4/085 takes precedence)}
- H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10)

## Abstract

A ceramic electronic component includes a multilayer chip having a substantially rectangular parallelepiped shape and including dielectric layers and internal electrode layers that are alternately stacked, a main component of the dielectric layers being ceramic, a main component of the internal electrode layers being Ni, the internal electrode layers being alternately exposed to two end faces of the multilayer chip opposite to each other, and external electrodes, each of which is provided on each of the two end faces. Each of the external electrodes includes a base layer contacting the internal electrode layers, a main component of the base layer being Cu. The base layer includes Ni of 1 wt % or more and 10 wt % or less on a presumption that an amount of Cu is 100 wt %.

## Claims

### Claim 1

A ceramic electronic component device:
a multilayer chip having a substantially rectangular parallelepiped shape and including dielectric layers and internal electrode layers that are alternately stacked, a main component of the dielectric layers being ceramic, a main component of the internal electrode layers being Ni, the internal electrode layers being alternately exposed to two end faces of the multilayer chip opposite to each other; and
external electrodes, each of which is provided on each of the two end faces,
wherein each of the external electrodes includes a base layer contacting the internal electrode layers, a main component of the base layer being Cu, and
wherein the base layer includes Ni of 1 wt % or more and 5.0 wt % or less on a presumption that an amount of Cu is 100 wt %.

### Claim 2 (depends on 1)

The ceramic electronic device as claimed in claim 1, wherein the base layer includes an oxide including Ni and Zn.

### Claim 3 (depends on 1)

The ceramic electronic device as claimed in claim 1, wherein an average grain diameter of the oxide including Ni and Zn is 1 μm or less, in the base layer.

### Claim 4 (depends on 1)

The ceramic electronic device as claimed in claim 1, wherein the base layer includes a glass component of 7 weight parts or more and 13 weight parts or less with respect to Cu.

### Claim 5 (depends on 1)

The ceramic electronic device as claimed in claim 1, wherein the base layer includes Ni of 3 wt % or more on a presumption that the amount of Cu is 100 wt %.

### Claim 6 (depends on 1)

The ceramic electronic device as claimed in claim 1, wherein the base layer includes Ni of 5 wt % or more on a presumption that the amount of Cu is 100 wt %.

### Claim 7 (depends on 1)

The ceramic electronic device as claimed in claim 1, wherein the base layer includes Ni of 7 wt % or less on a presumption that the amount of Cu is 100 wt %.

### Claim 8

A manufacturing method of a ceramic electronic device comprising:
preparing a ceramic multilayer structure having a substantially rectangular parallelepiped shape in which dielectric green sheets including a main component ceramic and metal conductive pastes for internal electrode layers including Ni as a main component metal are alternately stacked, the metal conductive pastes being alternately exposed to two end faces of the ceramic multilayer structure opposite to each other;
forming a multilayer chip by firing the ceramic multilayer structure;
providing metal conductive pastes for base layers contacting the two end faces, a main component metal of the metal conductive paste for base layers being Cu powder, an amount of Ni powder of the metal conductive paste for base layers being 1 wt % or more and 5.0 wt % or less on a presumption that an amount of Cu is 100 wt %; and
firing the metal conductive pastes for base layers.

### Claim 9 (depends on 8)

The method as claimed in claim 8, wherein a temperature of the firing of the metal conductive pastes for base layers is 780° C. or more and 860° C. or less.

### Claim 10 (depends on 8)

The method as claimed in claim 8, wherein an average particle diameter of the Ni powder is 0.1 μm or more and 5 μm or less in the metal conductive pastes for the base layers.

### Claim 11 (depends on 8)

The method as claimed in claim 8, wherein an average particle diameter of the Cu powder is 0.5 μm or more and 10 μm or less in the metal conductive pastes for the base layers.

### Claim 12 (depends on 8)

The method as claimed in claim 8, wherein the amount of Ni powder of the metal conductive paste for base layers is 3 wt % or more on a presumption that the amount of Cu is 100 wt %.

### Claim 13 (depends on 8)

The method as claimed in claim 8, wherein the amount of Ni powder of the metal conductive paste for base layers is 5 wt % or more on a presumption that the amount of Cu is 100 wt %.

### Claim 14 (depends on 8)

The method as claimed in claim 8, wherein the amount of Ni powder of the metal conductive paste for base layers is 7 wt % or less on a presumption that the amount of Cu is 100 wt %.

### Claim 15

A ceramic electronic component device:
a multilayer chip having a substantially rectangular parallelepiped shape and including dielectric layers and internal electrode layers that are alternately stacked, a main component of the dielectric layers being ceramic, a main component of the internal electrode layers being Ni, the internal electrode layers being alternately exposed to two end faces of the multilayer chip opposite to each other; and
external electrodes, each of which is provided on each of the two end faces,
wherein each of the external electrodes includes a base layer contacting the internal electrode layers, a main component of the base layer being Cu, and
wherein the base layer includes Ni of 1 wt % or more and 10 wt % or less on a presumption that an amount of Cu is 100 wt %, and the base layer includes an oxide including Ni and Zn.

### Claim 16 (depends on 15)

The ceramic electronic device as claimed in claim 15, wherein an average grain diameter of the oxide including the Ni and the Zn is 1 μm or less, in the base layer.

### Claim 17

A manufacturing method of a ceramic electronic device comprising:
preparing a ceramic multilayer structure having a substantially rectangular parallelepiped shape in which dielectric green sheets including a main component ceramic and metal conductive pastes for internal electrode layers including Ni as a main component metal are alternately stacked, the metal conductive pastes being alternately exposed to two end faces of the ceramic multilayer structure opposite to each other;
forming a multilayer chip by firing the ceramic multilayer structure;
providing metal conductive pastes for base layers contacting the two end faces, a main component metal of the metal conductive paste for base layers being Cu powder, an amount of Ni powder of the metal conductive paste for base layers being 1 wt % or more and 10 wt % or less on a presumption that an amount of Cu is 100 wt %; and
firing the metal conductive pastes for base layers;
wherein the base layer includes an oxide including Ni and Zn.

### Claim 18 (depends on 17)

The ceramic electronic device as claimed in claim 17, wherein an average grain diameter of the oxide including the Ni and the Zn is 1 μm or less, in the base layer.