# US 12,112,891 B2 · Multilayer capacitor and circuit board containing the same

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- Number: US 12,112,891 B2
- Document ID: US12112891B2
- Status: Granted
- Kind: B2
- Application number: 17/890,650
- Filed: 2022-08-18
- Published: 2022-12-08
- Granted: 2024-10-08
- Earliest claimed: 2017-05-15
- Assignees: KYOCERA AVX Components Corporation
- Applicants: KYOCERA AVX Components Corporation
- Inventors: Jeffrey Cain
- Web page: https://patentgrep.com/patent/US12112891B2

## CPC

- H01G 4/1227: {based on alkaline earth titanates}
- H01G 4/005: Electrodes
- H01G 4/012: Form of non-self-supporting electrodes
- H01G 4/232: electrically connecting two or more layers of a stacked or rolled capacitor
- H01G 4/252: the terminals being coated on the capacitive element (H01G4/232 takes precedence)
- H01G 4/30: Stacked capacitors (H01G4/33 takes precedence)
- H05K 1/181: associated with surface mounted components
- H05K 1/0231: {Capacitors or dielectric substances}
- H05K 3/3436: {having an array of bottom contacts, e.g. pad grid array or ball grid array components}
- H05K 2201/10015: Non-printed capacitor
- H05K 2201/10515: Stacked components
- H05K 2201/1053: Mounted components directly electrically connected to each other, i.e. not via the PCB
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/798: {between a chip and a stacked discrete passive device}
- Y02P 70/50: Manufacturing or production processes characterised by the final manufactured product
- H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10)
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS

## Abstract

The present invention is directed to a multilayer capacitor and a circuit board containing the multilayer capacitor. The capacitor includes a main body containing a first set of alternating dielectric layers and internal electrode layers and a second set of alternating dielectric layers and internal electrode layers. Each set contains a first internal electrode layer and a second internal electrode layer wherein each layer includes a top edge, a bottom edge opposite the top edge, and two side edges that define a main body of the layer. Each layer contains at least one lead tab extending from the top edge of the main body of the layer and at least one lead tab extending from the bottom edge of the main body of the layer wherein the lead tabs are offset from the side edges of the main body of the layer. In addition, external terminals are electrically connected to the internal electrode layers wherein the external terminals are formed on a top surface of the capacitor and a bottom surface of the capacitor opposing the top surface of the capacitor.

## Claims

### Claim 1

A component comprising:
a circuit board;
an integrated circuit package, and
a multilayer capacitor positioned between the circuit board and the integrated circuit package, wherein the multilayer capacitor comprises
a main body containing a first set of alternating dielectric layers and internal electrode layers and a second set of alternating dielectric layers and internal electrode layers, each set of alternating dielectric layers and internal electrode layers containing a first internal electrode layer and a second internal electrode layer, wherein the first set is separated from the second set by a distance greater than a thickness of an individual dielectric layer,
first external terminals electrically connected to the internal electrode layers of the first set and second external terminals electrically connected to the internal electrode layers of the second set, wherein the first external terminals and the second external terminals are formed on a top surface of the capacitor and a bottom surface of the capacitor opposing the top surface of the capacitor, and
wherein the first external terminals and the second external terminals on the top surface of the multilayer capacitor are directly connected to the integrated circuit package and wherein the first external terminals and the second external terminals on the bottom surface of the multilayer capacitor are directly connected to the circuit board.

### Claim 2 (depends on 1)

The component according to claim 1, wherein each internal electrode layer includes a top edge, a bottom edge opposite the top edge, and two side edges extending between the top edge and the bottom edge that define a main body of the internal electrode layer.

### Claim 3 (depends on 2)

The component according to claim 2, wherein each internal electrode layer includes at least one lead tab extending from the top edge of the main body of the internal electrode layer and at least one lead tab extending from the bottom edge of the main body of the internal electrode layer.

### Claim 4 (depends on 3)

The component according to claim 3, wherein at least one lateral edge of the lead tab on the top edge is substantially aligned with at least one lateral edge of the lead tab on the bottom edge.

### Claim 5 (depends on 3)

The component according to claim 3, wherein both lateral edges of the lead tab on the top edge are substantially aligned with both lateral edges of the lead tab on the bottom edge.

### Claim 6 (depends on 3)

The component according to claim 3, wherein the lead tab extending from the top edge of the main body of the internal electrode layer is offset from the side edge of the main body of the internal electrode layer.

### Claim 7 (depends on 3)

The component according to claim 3, wherein the lead tab extending from the bottom edge of the main body of the internal electrode layer is offset from the side edge of the main body of the internal electrode layer.

### Claim 8 (depends on 2)

The component according to claim 2, wherein each internal electrode layer includes at least two lead tabs extending from the top edge, the bottom edge, or both the top edge and the bottom edge, the two lead tabs including a first lead tab and a second lead tab.

### Claim 9 (depends on 8)

The component according to claim 8, wherein at least one lateral edge of the first lead tab and at least one lateral edge of the second lead tab on a top edge are substantially aligned with at least one lateral edge of the first lead tab and at least one lateral edge of the second lead tab on a bottom edge respectively.

### Claim 10 (depends on 8)

The component according to claim 8, wherein both lateral edges of the first lead tab and both lateral edges of the second lead tab on a top edge are substantially aligned with both lateral edges of the first lead tab and both lateral edges of a second lead tab on the bottom edge.

### Claim 11 (depends on 1)

The component according to claim 1, wherein the first internal electrode layer and the second internal electrode layer are interleaved in an opposed relation and a dielectric layer is positioned between the first internal electrode layer and the second internal electrode layer.

### Claim 12 (depends on 1)

The component according to claim 1, wherein the dielectric layers comprise a ceramic.

### Claim 13 (depends on 1)

The component according to claim 1, wherein the internal electrode layers comprise a conductive metal.

### Claim 14 (depends on 1)

The component according to claim 1, wherein the external terminals include an electroplated layer.

### Claim 15 (depends on 1)

The component according to claim 1, wherein the external terminals include an electroless plated layer.

### Claim 16 (depends on 1)

The component according to claim 1, wherein the external terminals include an electroless plated layer and an electroplated layer.

### Claim 17 (depends on 1)

The component according to claim 1, wherein the external terminals include a first electroless plated layer, a second electroplated layer, and a third electroplated layer.

### Claim 18 (depends on 17)

The component according to claim 17, wherein the first electroless plated layer includes copper, the second electroplated layer includes nickel, and the third electroplated layer includes tin.

### Claim 19 (depends on 1)

The component according to claim 1, wherein the capacitor includes at least three sets of alternating dielectric layers and internal electrode layers.

### Claim 20 (depends on 1)

The component according to claim 1, wherein the capacitor is directly connected to the circuit board and the integrated circuit package.

### Claim 21 (depends on 1)

The component according to claim 1, wherein the capacitor is embedded into the integrated circuit package.

### Claim 22 (depends on 1)

The component according to claim 1, wherein the circuit board further comprises a processor connected to the integrated circuit package.
