# US 12,112,831 B2 · Memory row-hammer mitigation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,112,831 B2 - Document ID: US12112831B2 - Status: Granted - Kind: B2 - Application number: 17/877,592 - Filed: 2022-07-29 - Published: 2024-02-01 - Granted: 2024-10-08 - Earliest claimed: 2022-07-29 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Bryan David Kerstetter; Alan J. Wilson; Donald Martin Morgan - Web page: https://patentgrep.com/patent/US12112831B2 ## CPC - G11C 7/24: Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells - G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals} - G11C 7/1066: {Output synchronization} - G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management - G11C 8/20: Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access - G11C 11/2295: {Protection circuits or methods} - G11C 16/22: Safety or protection circuits preventing unauthorised or accidental access to memory cells - G11C 16/30: Power supply circuits - G11C 16/32: Timing circuits - G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 7/02: with means for avoiding parasitic signals - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Methods, systems, and devices for memory row-hammer mitigation are described. A memory device may operate based on a scheme that is continuous across power cycles. For example, the memory device may access a region if a value of a counter does not satisfy a threshold value and may access the region if a value of the counter satisfies the threshold value. Upon transitioning power states, the value of the counter may be stored to a non-volatile memory such that it may be accessed when transitioning back to the original power state (e.g., an “ON” state). Accordingly, the value of the counter may be maintained across power cycles. ## Claims ### Claim 1 A method, comprising: transitioning, by a memory device comprising a first non-volatile memory and a second non-volatile memory, from a second power state to a first power state; receiving, based at least in part on transitioning from the second power state to the first power state, a command to access a region of the second non-volatile memory; reading a value of a counter stored to the first non-volatile memory based at least in part on receiving the command to access the region of the second non-volatile memory, wherein the value of the counter is associated with a quantity of access operations performed on the second non-volatile memory before transitioning from the second power state to the first power state; and refraining from accessing the region of the second non-volatile memory based at least in part on the value of the counter stored to the first non-volatile memory satisfying a threshold value. ### Claim 2 (depends on 1) The method of claim 1, further comprising: receiving a second command to perform a memory management operation on at least the region of the second non-volatile memory while operating in the first power state; and decrementing the value of the counter based at least in part on receiving the second command to perform the memory management operation. ### Claim 3 (depends on 2) The method of claim 2, further comprising: receiving, based at least in part on decrementing the value of the counter, a third command to access the region of the second non-volatile memory; reading the value of the counter stored to the first non-volatile memory based at least in part on receiving the third command to access the region of the second non-volatile memory; and accessing the region of the second non-volatile memory based at least in part on the value of the counter not satisfying the threshold value. ### Claim 4 (depends on 3) The method of claim 3, further comprising: determining that the value of the counter does not satisfy the threshold value based at least in part on reading the value of the counter, wherein the accessing the region of the second non-volatile memory is based at least in part on determining that the value of the counter does not satisfy the threshold value. ### Claim 5 (depends on 3) The method of claim 3, further comprising: updating the value of the counter based at least in part on accessing the region of the second non-volatile memory. ### Claim 6 (depends on 1) The method of claim 1, further comprising: receiving a fourth command to transition from the first power state to the second power state; and storing the value of the counter to the first non-volatile memory based at least in part on receiving the command to transition from the first power state to the second power state. ### Claim 7 (depends on 1) The method of claim 1, further comprising: determining that the value of the counter satisfies the threshold value based at least in part on reading the value of the counter, wherein the refraining from accessing the region of the second non-volatile memory is based at least in part on determining that the value of the counter satisfies the threshold value. ### Claim 8 (depends on 1) The method of claim 1, wherein the first non-volatile memory comprises a register for storing the value of the counter. ### Claim 9 (depends on 1) The method of claim 1, wherein the first power state comprises a higher power state than the second power state. ### Claim 10 A method, comprising: receiving, at a memory device comprising a first non-volatile memory and a second non-volatile memory, a command to access a region of the second non-volatile memory; updating a value of a counter associated with the region of the second non-volatile memory based at least in part on receiving the command to access the region of the second non-volatile memory, wherein the value of the counter is associated with a quantity of access operations performed on the region of the second non-volatile memory before transitioning from a first power state to a second power state; receiving, after updating the value of the counter associated with the memory device, a command to transition from the first power state to the second power state; and storing the value of the counter to the first non-volatile memory based at least in part on receiving the command to transition from the first power state to the second power state, the value stored to the first non-volatile memory indicating whether to perform an access operation on the region of the second non-volatile memory upon transitioning from the second power state to the first power state. ### Claim 11 (depends on 10) The method of claim 10, further comprising: receiving a second command to transition from the second power state to the first power state; receiving a third command to access the region of the second non-volatile memory based at least in part on transitioning from the second power state to the first power state; reading the value of the counter stored to the first non-volatile memory based at least in part on receiving the third command to access the region of the second non-volatile memory; and refraining from accessing the region of the second non-volatile memory based at least in part on the value of the counter satisfying a threshold value. ### Claim 12 (depends on 11) The method of claim 11, further comprising: receiving a fourth command to perform a memory management operation while operating in the first power state; and decrementing, based at least in part on receiving the fourth command to perform the memory management operation, the value of the counter to obtain a second value, wherein the second value is a decremented value. ### Claim 13 (depends on 12) The method of claim 12, further comprising: receiving, based at least in part on obtaining the second value, a fifth command to access the region of the second non-volatile memory; reading the second value of the counter stored to the first non-volatile memory based at least in part on receiving the fifth command to access the region of the second non-volatile memory; and accessing the region of the second non-volatile memory based at least in part on the second value of the counter not satisfying the threshold value. ### Claim 14 (depends on 13) The method of claim 13, further comprising: determining that the second value of the counter does not satisfy the threshold value based at least in part on reading the second value of the counter from the first non-volatile memory, wherein the accessing the region of the second non-volatile memory is based at least in part on determining that the second value of the counter does not satisfy the threshold value. ### Claim 15 (depends on 10) The method of claim 10, further comprising: determining that the value of the counter does not satisfy a threshold value based at least in part on receiving the command to access the region of the second non-volatile memory; and accessing the region of the second non-volatile memory based at least in part on determining that the value of the counter does not satisfy the threshold value, wherein the updating the value of the counter is based at least in part on determining that the value of the counter does not satisfy the threshold value. ### Claim 16 (depends on 10) The method of claim 10, wherein the first non-volatile memory comprises a register for storing the value of the counter. ### Claim 17 (depends on 10) The method of claim 10, wherein the first power state comprises a higher power state than the second power state. ### Claim 18 An apparatus comprising: a memory device; and a controller coupled with the memory device, the controller configured to cause the apparatus to: transition, by the memory device comprising a first non-volatile memory and a second non-volatile memory, from a second power state to a first power state; receiving, based at least in part on transitioning from the second power state to the first power state, a command to access a region of the second non-volatile memory; reading a value of a counter stored to the first non-volatile memory based at least in part on receiving the command to access the region of the second non-volatile memory, wherein the value of the counter is associated with a quantity of access operations performed on the second non-volatile memory before transitioning from the second power state to the first power state; and refraining from accessing the region of the second non-volatile memory based at least in part on the value of the counter stored to the first non-volatile memory satisfying a threshold value. ### Claim 19 (depends on 18) The apparatus of claim 18, wherein the controller is further configured to cause the apparatus to: receive a second command to perform a memory management operation on at least the region of the second non-volatile memory while operating in the first power state; and decrement the value of the counter based at least in part on receiving the second command to perform the memory management operation. ### Claim 20 (depends on 19) The apparatus of claim 19, wherein the controller is further configured to cause the apparatus to: receive, based at least in part on decrementing the value of the counter, a third command to access the region of the second non-volatile memory; read the value of the counter stored to the first non-volatile memory based at least in part on receiving the third command to access the region of the second non-volatile memory; and access the region of the second non-volatile memory based at least in part on the value of the counter not satisfying the threshold value. ### Claim 21 (depends on 20) The apparatus of claim 20, wherein the controller is further configured to cause the apparatus to: determine that the value of the counter does not satisfy the threshold value based at least in part on reading the value of the counter, wherein the accessing the region of the second non-volatile memory is based at least in part on determining that the value of the counter does not satisfy the threshold value. ### Claim 22 An apparatus, comprising: a memory device; and a controller coupled with the memory device, the controller configured to cause the apparatus to: receive, at the memory device comprising a first non-volatile memory and a second non-volatile memory, a command to access a region of the second non-volatile memory; update a value of a counter associated with the region of the second non-volatile memory based at least in part on receiving the command to access the region of the second non-volatile memory, wherein the value of the counter is associated with a quantity of access operations performed on the region of the second non-volatile memory before transitioning from a first power state to a second power state; receive, after updating the value of the counter associated with the memory device, a command to transition from the first power state to the second power state; and store the value of the counter to the first non-volatile memory based at least in part on receiving the command to transition from the first power state to the second power state, the value stored to the first non-volatile memory indicating whether to perform an access operation on the region of the second non-volatile memory upon transitioning from the second power state to the first power state. ### Claim 23 (depends on 22) The apparatus of claim 22, wherein the controller is further configured to cause the apparatus to: receive a second command to transition from the second power state to the first power state; receive, based at least in part on transitioning from the second power state to the first power state, a third command to access the region of the second non-volatile memory; read the value of the counter stored to the first non-volatile memory based at least in part on receiving the third command to access the region of the second non-volatile memory; and refrain from accessing the region of the second non-volatile memory based at least in part on the value of the counter satisfying a threshold value. ### Claim 24 (depends on 23) The apparatus of claim 23, wherein the controller is further configured to cause the apparatus to: receive a fourth command to perform a memory management operation while operating in the first power state; and decrement, based at least in part on receiving the fourth command to perform the memory management operation, the value of the counter to obtain a second value, wherein the second value is a decremented value. ### Claim 25 (depends on 24) The apparatus of claim 24, wherein the controller is further configured to cause the apparatus to: receive, based at least in part on obtaining the second value of the counter, a fifth command to access the region of the second non-volatile memory; read the second value of the counter stored to the first non-volatile memory based at least in part on receiving the fifth command to access the region of the second non-volatile memory; and access the region of the second non-volatile memory based at least in part on the second value of the counter not satisfying the threshold value.