# US 12,112,830 B2 · Methods for memory power management and memory devices and systems employing the same

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- Number: US 12,112,830 B2
- Document ID: US12112830B2
- Status: Granted
- Kind: B2
- Application number: 17/991,489
- Filed: 2022-11-21
- Published: 2023-03-16
- Granted: 2024-10-08
- Earliest claimed: 2019-08-02
- Applicants: Lodestar Licensing Group LLC
- Inventors: Eric J. Stave; George E. Pax; Yogesh Sharma; Gregory A. King; Chan H. Yoo; Randon K. Richards; Timothy M. Hollis
- Web page: https://patentgrep.com/patent/US12112830B2

## CPC

- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories}
- G11C 7/1093: {Input synchronization}
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 16/10: Programming or data input circuits
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.

## Claims

### Claim 1

A method comprising:
receiving, from a host at a component of a memory module, an indication of a duration corresponding to enabling an input buffer of a memory device of the memory module;
reducing, in response to receiving the indication of the duration, a programmable latency of the memory device by an amount corresponding to the duration;
receiving, from the host at the component of the memory module at a first time, an enable signal for the memory device;
receiving, from the host at the component at the first time, a command/address signal for the memory device;
sending the enable signal from the component to the memory device at a second time subsequent to the first time;
enabling a disabled input buffer of the memory device in response to detecting the enable signal; and
sending the command/address signal from the component to the memory device at a third time subsequent to the second time by a delay corresponding to the duration.

### Claim 2 (depends on 1)

The method of claim 1, wherein the delay corresponds to a number of clock cycles of the memory device.

### Claim 3 (depends on 1)

The method of claim 1, wherein receiving the enable signal for the memory device at the component of the memory module comprises receiving the enable signal at a registering clock driver (RCD) of the memory module.

### Claim 4 (depends on 1)

The method of claim 1, wherein receiving the command/address signal for the memory device at the component of the memory module comprises receiving the command/address signal at a registering clock driver (RCD) of the memory module.

### Claim 5 (depends on 1)

The method of claim 1, wherein sending the enable signal from the component at the second time comprises sending the enable signal from a registering clock driver (RCD) of the memory module to the memory device.

### Claim 6 (depends on 1)

The method of claim 1, wherein sending the command/address signal from the component at the third time comprises:
delaying the command/address signal for a number of clock cycles of the memory device; and
sending the command/address signal from a registering clock driver (RCD) of the memory module to the memory device.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
disabling the input buffer of the memory device prior to sending the enable signal at the second time.

### Claim 8 (depends on 1)

The method of claim 1, wherein enabling the disabled input buffer is complete before the third time.

### Claim 9 (depends on 1)

The method of claim 1, wherein the enable signal is a chip select (CS) signal.

### Claim 10

A memory module, comprising:
a memory device; and
a registering clock driver (RCD) coupled to the memory device and configured to:
receive an indication of a duration corresponding to enabling an input buffer of the memory device;
receive an enable signal and a command/address signal at a first time,
send the enable signal to the memory device at a second time subsequent to the first time, and
send the command/address signal to the memory device at a third time subsequent to the second time by a delay corresponding to the duration,
wherein the memory device is configured to:
reduce, in response to the RCD receiving the indication of the duration, a programmable latency of the memory device by an amount corresponding to the duration; and
enable a disabled input buffer in response to detecting the enable signal.

### Claim 11 (depends on 10)

The memory module of claim 10, wherein the delay corresponds to a number of clock cycles of the memory device.

### Claim 12 (depends on 10)

The memory module of claim 10, wherein the memory device is further configured to:
disable the input buffer in response to a determination that the memory device is idle.

### Claim 13 (depends on 10)

The memory module of claim 10, wherein the memory device is configured to complete enabling the disabled input buffer before the third time.

### Claim 14 (depends on 10)

The memory module of claim 10, wherein the memory device comprises a dynamic random access memory (DRAM) device.

### Claim 15 (depends on 10)

The memory module of claim 10, wherein the memory module comprises a dual in-line memory module (DIMM).

### Claim 16

A memory device, comprising:
an input buffer; and
circuitry coupled to the input buffer and configured to:
reduce a programmable latency of the memory device by an amount corresponding to a duration that corresponds to enabling the input buffer;
disable the input buffer in response to a determination that the memory device is idle;
re-enable the input buffer in response to detecting an enable signal received at the memory device at a first time; and
receive a command/address signal at a second time subsequent to the first time by a delay corresponding to the duration.

### Claim 17 (depends on 16)

The memory device of claim 16, wherein the memory device comprises a dynamic random access memory (DRAM) device.

### Claim 18 (depends on 16)

The memory device of claim 16, wherein the memory device comprises a dual in-line memory module (DIMM).