# US 12,112,829 B2 · Memory array circuits, memory structures, and methods for fabricating a memory array circuit

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- Number: US 12,112,829 B2
- Document ID: US12112829B2
- Status: Granted
- Kind: B2
- Application number: 17/575,397
- Filed: 2022-01-13
- Published: 2023-05-25
- Granted: 2024-10-08
- Earliest claimed: 2021-11-24
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chun-Ying Lee; Chia-En Huang; Meng-Sheng Chang
- Web page: https://patentgrep.com/patent/US12112829B2

## CPC

- G11C 7/14: Dummy cell management; Sense reference voltage generators
- G11C 17/16: using electrically-fusible links
- G11C 7/18: Bit line organisation; Bit line lay-out
- G11C 17/18: Auxiliary circuits, e.g. for writing into memory
- H10D 89/10: Integrated device layouts
- H10W 90/00: Package configurations
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- H10B 12/056: {the transistor being a FinFET}
- H10B 12/36: {the transistor being a FinFET}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A memory array circuit includes a memory array and a set of dummy cells surrounding the memory array. The first memory array includes a first set of memory cells located in an inner area of the memory array and a second set of memory cells located along an edge of the memory array. Each dummy cell includes one or more active regions and multiple gate structures over the one or more active regions.

## Claims

### Claim 1

A memory array circuit, comprising:
a first memory array, including:
a first set of memory cells located in an inner area of the first memory array; and
a second set of memory cells located along an edge of the first memory array, wherein a first channel length of a first transistor in the first set of memory cells is less than a second channel length of a second transistor in the second set of memory cells; and
a set of dummy cells surrounding the first memory array, wherein each dummy cell includes one or more active regions and a plurality of gate structures over the one or more active regions, wherein the gate structures in the dummy cells and gate structures of the memory cells have the same width.

### Claim 2 (depends on 1)

The memory array circuit of claim 1, wherein the number of the active regions within one dummy cell is the same or a multiple of the number of the active regions within one of the memory cells of the first or second sets of memory cells.

### Claim 3 (depends on 1)

The memory array circuit of claim 1, wherein each dummy cell includes a plurality of dummy transistors.

### Claim 4 (depends on 1)

The memory array circuit of claim 1, further comprising:
a second memory array, including:
a third set of memory cells located in an inner area of the second memory array; and
a fourth set of memory cells located along an edge of the second memory array;
wherein the set of dummy cells comprises:
a plurality of first dummy cells surrounding the first memory array; and
a plurality of second dummy cells surrounding the second memory array.

### Claim 5 (depends on 4)

The memory array circuit of claim 4, wherein the first dummy cells and the second dummy cells share one or more cells located between adjacent edges of the first memory array and the second memory array.

### Claim 6 (depends on 4)

The memory array circuit of claim 4, wherein bit lines of the first memory array are aligned with respect to bit lines of the second memory array.

### Claim 7 (depends on 1)

The memory array circuit of claim 1, wherein each memory cell includes a predetermined number of transistors.

### Claim 8 (depends on 7)

The memory array circuit of claim 7, wherein each memory cell is coupled to a word line of the memory array circuit, by one or more corresponding transistors within the memory cell.

### Claim 9 (depends on 7)

The memory array circuit of claim 7, wherein each memory cell is coupled to a select line of the memory array circuit, by one or more corresponding transistors within the memory cell.

### Claim 10 (depends on 7)

The memory array circuit of claim 7, further comprising:
one or more dummy transistors located between two adjacent memory cells, the one or more dummy transistors being coupled to one or more corresponding transistors within each of the two adjacent memory cells.

### Claim 11

A memory structure, comprising:
a plurality of memory cells forming a memory array, wherein a first channel length of a first transistor in a first set of memory cells located in an inner area of the memory array is less than a second channel length of a second transistor in a second set of memory cells located along an edge of the memory array, at least one of the memory cells comprising:
a plurality of active regions extending in a first direction; and
a plurality of gate structures disposed over the plurality of active regions and extending in a second direction; and
a plurality of dummy cells surrounding the memory array, at least one of the dummy cells comprising:
one or more dummy active regions extending in the first direction; and
a plurality of dummy gate structures disposed over the one or more active regions and extending in the second direction, wherein the dummy gate structures and the gate structures of the memory cells have the same width.

### Claim 12 (depends on 11)

The memory structure of claim 11, wherein the number of the dummy active regions within one dummy cell is the same or a multiple of the number of the active regions within one memory cell.

### Claim 13 (depends on 11)

The memory structure of claim 11, wherein at least one of the dummy cells further comprises one or more conductive layers having one or more conductive features.

### Claim 14 (depends on 11)

The memory structure of claim 11, wherein at least one of the memory cells further comprises one or more conductive layers having one or more conductive features coupled to one or more transistors formed by the active regions and the gate structures in the memory cell.

### Claim 15 (depends on 11)

The memory structure of claim 11, wherein the memory array comprises:
a first sub-array comprising a plurality of first memory cells;
a second sub-array comprising a plurality of second memory cells; and
a plurality of shared dummy cells located between an edge of the first sub-array and an edge of the second sub-array and configured to separate the first sub-array and the second sub-array.

### Claim 16 (depends on 15)

The memory structure of claim 15, wherein bit lines of the first sub-array are aligned with respect to bit lines of the second sub-array.

### Claim 17

A method for fabricating a memory array circuit, the method comprising:
forming a plurality of memory cells of a first memory array, wherein a first channel length of a first transistor in a first set of memory cells located in an inner area of the first memory array is less than a second channel length of a second transistor in a second set of memory cells located along an edge of the first memory array; and
forming a plurality of dummy cells surrounding the first memory array, by providing one or more active regions and a plurality of gate structures, wherein each of the dummy cells includes the one or more active regions and the plurality of gate structures over the one or more active regions, wherein the gate structures in the dummy cells and the gate structures in the memory cells have the same width.

### Claim 18 (depends on 17)

The method of claim 17, wherein the number of the active regions within one dummy cell is the same or a multiple of the number of the active regions within one of the memory cells.

### Claim 19 (depends on 17)

The method of claim 17, wherein forming the plurality of dummy cells comprises:
forming the one or more active regions extending in a first direction; and
forming the plurality of gate structures disposed over the one or more active regions and extending in a second direction.

### Claim 20 (depends on 17)

The method of claim 17, wherein the memory cells are first memory cells and the dummy cells are first dummy cells, the method further comprising:
forming a plurality of second memory cells of a second memory array adjacent to the first memory array; and
forming a plurality of second dummy cells surrounding the second memory array, wherein the first dummy cells and the second dummy cells share a plurality of cells located between an edge of the first memory array and an edge of the second memory array.