# US 12,112,828 B2 · Modification of a command timing pattern

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- Number: US 12,112,828 B2
- Document ID: US12112828B2
- Status: Granted
- Kind: B2
- Application number: 17/938,002
- Filed: 2022-10-04
- Published: 2023-05-25
- Granted: 2024-10-08
- Earliest claimed: 2021-11-24
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Carl L. Minifie; Phong T. Nguyen; Alexander A. Tomaso
- Web page: https://patentgrep.com/patent/US12112828B2

## CPC

- G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals}
- G11C 7/109: {Control signal input circuits}
- G11C 7/1069: {I/O lines read out arrangements}
- G11C 7/1093: {Input synchronization}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Methods, systems, and devices for modification of a command timing pattern are described. A host device may transmit (e.g., issue), to a memory device, a quantity of deselect commands between activation or data access commands to satisfy configured timing constraints. Each deselect command may indicate a polarity (e.g., a high voltage or a low voltage) for a command and address (CA) pin at the memory device. In some examples, the quantity of deselect commands may include one or more sequences of deselect commands (e.g., low-high-high-high). The host device may truncate a sequence of deselect commands, for example to satisfy timing constraints without transmitting additional unnecessary commands. By dynamically configuring the quantity of deselect commands, the host device may improve latency and overall efficiency of system operations without violating the configured timing constraints.

## Claims

### Claim 1

A method, comprising:
receiving a first activation command to activate a first set of memory cells in a first bank of a memory device;
receiving, based at least in part on the first activation command, a quantity of deselect commands, the quantity of deselect commands based at least in part on one or both of a row activation command delay or a column activation command delay, and based at least in part on one or both of a row address to column address delay or an activation command window; and
receiving, based at least in part on the deselect commands, a second activation command to activate a second set of memory cells in a second bank of the memory device.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
receiving, after receiving the first activation command and after a duration that is based at least in part on the row address to column address delay, a read command associated with the first bank of the memory device.

### Claim 3 (depends on 1)

The method of claim 1, wherein the second activation command is received within the activation command window, the method further comprising:
receiving, within the activation command window, a third activation command to activate a third set of memory cells in a third bank of the memory device;
receiving, within the activation command window, a fourth activation command to activate a fourth set of memory cells in a fourth bank of the memory device; and
receiving, after receiving the first activation command and after the activation command window, a fifth activation command to activate a fifth set of memory cells in a fifth bank of the memory device.

### Claim 4 (depends on 1)

The method of claim 1, wherein the deselect commands comprise a sequence of deselect commands.

### Claim 5 (depends on 4)

The method of claim 4, wherein the sequence of deselect commands comprises a first deselect command indicating a first polarity for a command/address pin and a second deselect command indicating a second polarity for the command/address pin.

### Claim 6 (depends on 4)

The method of claim 4, wherein:
the sequence of deselect commands is truncated based at least in part on one or both of the row activation command delay or the column activation command delay, and
the sequence of deselect commands is truncated based at least in part on one or both of the row address to column address delay or the activation command window.

### Claim 7 (depends on 1)

The method of claim 1, wherein:
the second bank is in a different bank group than the first bank;
the row activation command delay comprises a shortened row activation command delay based at least in part on the second bank being in a different bank group than the first bank; and
the column activation command delay comprises a shortened column activation command delay based at least in part on the second bank being in a different bank group than the first bank.

### Claim 8

A method, comprising:
transmitting a first activation command to activate a first set of memory cells in a first bank of a memory device;
transmitting, based at least in part on the first activation command, a quantity of deselect commands, the quantity of deselect commands based at least in part on one or both of a row activation command delay or a column activation command delay, and based at least in part on one or both of a row address to column address delay or an activation command window; and
transmitting, based at least in part on the deselect commands, a second activation command to activate a second set of memory cells in a second bank of the memory device.

### Claim 9 (depends on 8)

The method of claim 8, further comprising:
transmitting, after transmitting the first activation command and after a duration that is based at least in part on the row address to column address delay, a read command associated with the first bank of the memory device.

### Claim 10 (depends on 8)

The method of claim 8, wherein the second activation command is transmitted within the activation command window, the method further comprising:
transmitting, within the activation command window, a third activation command to activate a third set of memory cells in a third bank of the memory device;
transmitting, within the activation command window, a fourth activation command to activate a fourth set of memory cells in a fourth bank of the memory device; and
transmitting, after transmitting the first activation command and after the activation command window, a fifth activation command to activate a fifth set of memory cells in a fifth bank of the memory device.

### Claim 11 (depends on 8)

The method of claim 8, wherein the deselect commands comprise a sequence of deselect commands.

### Claim 12 (depends on 11)

The method of claim 11, wherein the sequence of deselect commands comprises a first deselect command indicating a first polarity for a command/address pin of the memory device and a second deselect command indicating a second polarity for the command/address pin of the memory device.

### Claim 13 (depends on 11)

The method of claim 11, further comprising:
truncating the sequence of deselect commands based at least in part on one or both of the row activation command delay or the column activation command delay, and based at least in part on one or both of the row address to column address delay or the activation command window.

### Claim 14 (depends on 8)

The method of claim 8, wherein:
the second bank is in a different bank group than the first bank;
the row activation command delay comprises a shortened row activation command delay based at least in part on the second bank being in a different bank group than the first bank; and
the column activation command delay comprises a shortened column activation command delay based at least in part on the second bank being in a different bank group than the first bank.

### Claim 15

An apparatus, comprising:
a controller coupled with a memory device and configured to cause the apparatus to:
receive a first activation command to activate a first set of memory cells in a first bank of the memory device;
receive, based at least in part on the first activation command, a quantity of deselect commands, the quantity of deselect commands based at least in part on one or both of a row activation command delay or a column activation command delay, and based at least in part on one or both of a row address to column address delay or an activation command window; and
receive, based at least in part on the deselect commands, a second activation command to activate a second set of memory cells in a second bank of the memory device.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the controller is further configured to cause the apparatus to:
receive, after receiving the first activation command and after a duration that is based at least in part on the row address to column address delay, a read command associated with the first bank of the memory device.

### Claim 17 (depends on 15)

The apparatus of claim 15, wherein the second activation command is received within the activation command window, and wherein the controller is further configured to cause the apparatus to:
receive, within the activation command window, a third activation command to activate a third set of memory cells in a third bank of the memory device;
receive, within the activation command window, a fourth activation command to activate a fourth set of memory cells in a fourth bank of the memory device; and
receive, after receiving the first activation command and after the activation command window, a fifth activation command to activate a fifth set of memory cells in a fifth bank of the memory device.

### Claim 18 (depends on 15)

The apparatus of claim 15, wherein the deselect commands comprise a sequence of deselect commands.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein the sequence of deselect commands comprises a first deselect command indicating a first polarity for a command/address pin and a second deselect command indicating a second polarity for the command/address pin.

### Claim 20 (depends on 18)

The apparatus of claim 18, wherein:
the sequence of deselect commands is truncated based at least in part on one or both of the row activation command delay or the column activation command delay, and
the sequence of deselect commands is truncated based at least in part on one or both of the row address to column address delay or the activation command window.

### Claim 21 (depends on 15)

The apparatus of claim 15, wherein:
the second bank is in a different bank group than the first bank;
the row activation command delay comprises a shortened row activation command delay based at least in part on the second bank being in a different bank group than the first bank; and
the column activation command delay comprises a shortened column activation command delay based at least in part on the second bank being in a different bank group than the first bank.

### Claim 22

An apparatus, comprising:
a controller coupled with a host device, wherein the controller is configured to cause the apparatus to:
transmit a first activation command to activate a first set of memory cells in a first bank of a memory device;
transmit, based at least in part on the first activation command, a quantity of deselect commands, the quantity of deselect commands based at least in part on one or both of a row activation command delay or a column activation command delay, and based at least in part on one or both of a row address to column address delay or an activation command window; and
transmit, based at least in part on the deselect commands, a second activation command to activate a second set of memory cells in a second bank of the memory device.

### Claim 23 (depends on 22)

The apparatus of claim 22, wherein the controller is further configured to cause the apparatus to:
transmit, after transmitting the first activation command and after a duration that is based at least in part on the row address to column address delay, a read command associated with the first bank of the memory device.

### Claim 24 (depends on 22)

The apparatus of claim 22, wherein the second activation command is transmitted within the activation command window, and the controller is further configured to cause the apparatus to:
transmit, within the activation command window, a third activation command to activate a third set of memory cells in a third bank of the memory device;
transmit, within the activation command window, a fourth activation command to activate a fourth set of memory cells in a fourth bank of the memory device; and
transmit, after transmitting the first activation command and after the activation command window, a fifth activation command to activate a fifth set of memory cells in a fifth bank of the memory device.

### Claim 25 (depends on 22)

The apparatus of claim 22, wherein the deselect commands comprise a sequence of deselect commands.

### Claim 26 (depends on 25)

The apparatus of claim 25, wherein the sequence of deselect commands comprises a first deselect command indicating a first polarity for a command/address pin of the memory device and a second deselect command indicating a second polarity for the command/address pin of the memory device.

### Claim 27 (depends on 25)

The apparatus of claim 25, wherein the controller is further configured to cause the apparatus to:
truncate the sequence of deselect commands based at least in part on one or both of the row activation command delay or the column activation command delay, and based at least in part on one or both of the row address to column address delay or the activation command window.

### Claim 28 (depends on 22)

The apparatus of claim 22, wherein:
the second bank is in a different bank group than the first bank;
the row activation command delay comprises a shortened row activation command delay based at least in part on the second bank being in a different bank group than the first bank; and
the column activation command delay comprises a shortened column activation command delay based at least in part on the second bank being in a different bank group than the first bank.

### Claim 29

A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to:
receive a first activation command to activate a first set of memory cells in a first bank of a memory device;
receive, based at least in part on the first activation command, a quantity of deselect commands, the quantity of deselect commands based at least in part on one or both of a row activation command delay or a column activation command delay, and based at least in part on one or both of a row address to column address delay or an activation command window; and
receive, based at least in part on the deselect commands, a second activation command to activate a second set of memory cells in a second bank of the memory device.

### Claim 30 (depends on 29)

The non-transitory computer-readable medium of claim 29, wherein the instructions are further executable by the processor to:
receive, after receiving the first activation command and after a duration that is based at least in part on the row address to column address delay, a read command associated with the first bank of the memory device.

### Claim 31 (depends on 29)

The non-transitory computer-readable medium of claim 29, wherein the second activation command is received within the activation command window, and wherein the instructions are further executable by the processor to:
receive, within the activation command window, a third activation command to activate a third set of memory cells in a third bank of the memory device;
receive, within the activation command window, a fourth activation command to activate a fourth set of memory cells in a fourth bank of the memory device; and
receive, after receiving the first activation command and after the activation command window, a fifth activation command to activate a fifth set of memory cells in a fifth bank of the memory device.

### Claim 32 (depends on 29)

The non-transitory computer-readable medium of claim 29, wherein the deselect commands comprise a sequence of deselect commands.

### Claim 33 (depends on 32)

The non-transitory computer-readable medium of claim 32, wherein the sequence of deselect commands comprises a first deselect command indicating a first polarity for a command/address pin and a second deselect command indicating a second polarity for the command/address pin.

### Claim 34 (depends on 32)

The non-transitory computer-readable medium of claim 32, wherein:
the sequence of deselect commands is truncated based at least in part on one or both of the row activation command delay or the column activation command delay, and
the sequence of deselect commands is truncated based at least in part on one or both of the row address to column address delay or the activation command window.

### Claim 35 (depends on 29)

The non-transitory computer-readable medium of claim 29, wherein:
the second bank is in a different bank group than the first bank;
the row activation command delay comprises a shortened row activation command delay based at least in part on the second bank being in a different bank group than the first bank; and
the column activation command delay comprises a shortened column activation command delay based at least in part on the second bank being in a different bank group than the first bank.