# US 12,112,822 B2 · Multi-channel memory device capable of switching redundancy memory blocks to replace failed memory block > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,112,822 B2 - Document ID: US12112822B2 - Status: Granted - Kind: B2 - Application number: 17/903,052 - Filed: 2022-09-06 - Published: 2023-07-06 - Granted: 2024-10-08 - Earliest claimed: 2022-01-03 - Assignees: Winbond Electronics Corp. - Applicants: Winbond Electronics Corp. - Inventors: Chih-Feng Lin - Web page: https://patentgrep.com/patent/US12112822B2 ## CPC - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G11C 29/781: {combined in a redundant decoder} - G11C 29/785: {with redundancy programming schemes} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A multi-channel memory device includes N first memory blocks, a first redundancy memory block, and N first interface circuits. Each of the first interface circuits is coupled to two of the first memory blocks and the first redundancy memory block. The first interface circuits respectively select N first selected memory blocks in the first memory block and the first redundancy memory block according to a plurality of first selection signals, where N is a positive integer greater than 1. ## Claims ### Claim 1 A multi-channel memory device, comprising: N first memory blocks, where N is a positive integer greater than 1; a first redundancy memory block; N first interface circuits, wherein each of the first interface circuits is coupled to two of the first memory blocks and the first redundancy memory block, and each of the first interface circuits selects each of N first selected memory blocks in the first memory blocks and the first redundancy memory block to be coupled to a plurality of first input and output interfaces according to a plurality of first selection signals; and a decoder coupled to the storage and generating the first selection signals according to decoded error information, wherein the decoder generates a plurality of power control signals according to the decoded error information, and each of the first interface circuits turns on or cuts off power of each of the first memory blocks and the first redundancy memory block according to each of the power control signals. ### Claim 2 (depends on 1) The multi-channel memory device according to claim 1, wherein an i-th first interface circuit selects an i-th first memory block or an i+1-th first memory block according to an i-th first selection signal to be coupled to an i-th first input and output interface, and i is a positive integer greater than 0 and less than N. ### Claim 3 (depends on 2) The multi-channel memory device according to claim 2, wherein an N-th first interface circuit selects an N-th first memory block or the first redundancy memory block according to an N-th first selection signal to be coupled to an N-th first input and output interface. ### Claim 4 (depends on 1) The multi-channel memory device according to claim 1, further comprising: a storage storing error information of an error status of each of the first memory blocks. ### Claim 5 (depends on 4) The multi-channel memory device according to claim 4, wherein when none of the memory blocks is failed, the power control signal corresponding to the first redundancy memory block is at a non-active logic level. ### Claim 6 (depends on 4) The multi-channel memory device according to claim 4, wherein when one of the memory blocks is failed, the power control signal corresponding to the first redundancy memory block is at an active logic level. ### Claim 7 (depends on 4) The multi-channel memory device according to claim 4, wherein the storage is a fuse circuit. ### Claim 8 (depends on 7) The multi-channel memory device according to claim 7, wherein circuit structures of the first redundant interface circuit and the second redundant interface circuit are the same as a circuit structure of each of the first interface circuits. ### Claim 9 (depends on 1) The multi-channel memory device according to claim 1, wherein power channel of a failed memory block of the first memory blocks is cut off according to the corresponding power control signal by the corresponding first interface circuit. ### Claim 10 (depends on 1) The multi-channel memory device according to claim 1, wherein the power control signals are respectively same as the corresponding selection signals. ### Claim 11 (depends on 1) The multi-channel memory device according to claim 1, further comprising: a first redundant interface circuit and a second redundant interface circuit, wherein the first interface circuits are disposed in a row, and the first redundant interface circuit and the second redundant interface circuit are disposed on two sides of the row, respectively. ### Claim 12 (depends on 1) The multi-channel memory device according to claim 1, wherein an i-th first interface circuit comprises: a first switch coupled between a corresponding i-th first memory block and a corresponding i-th first input and output interface and controlled by a reverse signal of a corresponding i-th first selection signal; and a second switch coupled between a corresponding i+1-th first memory block and the i-th first input and output interface and controlled by the i-th first selection signal, wherein on and off states of the first switch and the second switch are opposite, and i is a positive integer greater than 0 and less than N. ### Claim 13 (depends on 1) The multi-channel memory device according to claim 1, wherein an N-th first interface circuit comprises: a first switch coupled between a corresponding N-th first memory block and a corresponding N-th first input and output interface and controlled by a reverse signal of a corresponding N-th first selection signal; and a second switch coupled between the corresponding first redundancy memory block and the N-th first input and output interface and controlled by the N-th first selection signal, wherein on and off states of the first switch and the second switch are opposite. ### Claim 14 (depends on 1) The multi-channel memory device according to claim 1, further comprising: M second memory blocks, where M is a positive integer greater than 1; a second redundancy memory block; and M second interface circuits, wherein each of the second interface circuits is coupled to two of the second memory blocks and the second redundancy memory block, and the second interface circuits respectively select N second selected memory blocks in the second memory blocks and the second redundancy memory block to be coupled to a plurality of second input and output interfaces according to a plurality of second selection signals. ### Claim 15 (depends on 14) The multi-channel memory device according to claim 14, wherein N and M are equal or different. ### Claim 16 (depends on 1) The multi-channel memory device according to claim 1, wherein the first input and output interfaces are solder pads.