# US 12,112,820 B2 · Single event effect mitigation with smart-redundancy

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- Number: US 12,112,820 B2
- Document ID: US12112820B2
- Status: Granted
- Kind: B2
- Application number: 17/539,923
- Filed: 2021-12-01
- Published: 2023-06-01
- Granted: 2024-10-08
- Earliest claimed: 2021-12-01
- Assignees: University of Utah Research Foundation
- Applicants: University of Utah Research Foundation
- Inventors: Aurelien Alacchi; Pierre-Emmanuel Gaillardon
- Web page: https://patentgrep.com/patent/US12112820B2

## CPC

- G11C 29/4401: {for self repair}
- G11C 29/76: {using address translation or modifications}
- G11C 5/005: {Circuit means for protection against loss of information of semiconductor storage devices}
- G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits}
- G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/24: Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
- G11C 29/38: Response verification devices
- G11C 29/789: {using non-volatile cells or latches}
- H03K 19/0033: {Radiation hardening}
- G11C 2029/0409: {Online test}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Electronic devices and methods for single event effect mitigation are described. The device can include a processor, a memory cell, and an integrated particle sensor. The memory cell can comprise a substrate, a deep well coupled to the substrate, and a ground-coupled well coupled to the deep well. The integrated particle sensor can be coupled between the substrate and the deep well, and the ground-coupled well and the deep well. The integrated particle sensor can be operable to detect an ionizing particle generating the single event effect. The electronic device can be a field-programmable gate array. The method can include detecting an ionizing particle generating a single event effect at a memory cell of the electronic device, switching from the memory cell to a redundant memory cell associated with the memory cell when the single event effect is detected, and reconfiguring the memory cell based on the redundant memory cell.

## Claims

### Claim 1

A electronic device for single event effect mitigation, comprising:
a processor;
a memory cell comprising:
a substrate;
a deep well coupled to the substrate; and
a ground-coupled well coupled to the deep well;
an integrated particle sensor comprising one or more p-n junctions intentionally configured for actively detecting particle strikes, the integrated particle sensor coupled between:
the substrate and the deep well, and
the ground-coupled well and the deep well,
wherein the integrated particle sensor is operable to detect an ionizing radiation particle generating the single event effect and output a corresponding detection signal; and
a sensor conditioner coupled to directly receive the detection signal from the integrated particle sensor, wherein the sensor conditioner includes a current-to-voltage converter, an amplifier, and a pulse generator, and wherein the sensor conditioner is tuned to process the detection signal to generate a pulse and activate reconfiguration to a redundant memory cell when the single event effect occurs.

### Claim 2 (depends on 1)

The electronic device of claim 1, wherein the memory cell has a triple-quadruple well transistor design.

### Claim 3 (depends on 1)

The electronic device of claim 1, wherein the integrated particle sensor is operable to detect an ionizing particle less than 100 milliseconds after the single event effect occurs.

### Claim 4 (depends on 1)

The electronic device of claim 1, wherein the processor is configured to switch from the memory cell to a redundant memory cell associated with the memory cell when the single event effect occurs.

### Claim 5 (depends on 1)

The electronic device of claim 1, wherein a redundant memory cell associated with the memory cell is positioned at a threshold distance that prevents the ionizing particle from generating the single event effect in both the memory cell and the redundant memory cell.

### Claim 6 (depends on 1)

The electronic device of claim 1, wherein the processor is configured to switch from the memory cell to a redundant memory cell associated with the memory cell when a configuration memory bit is activated.

### Claim 7 (depends on 1)

The electronic device of claim 1, wherein the processor is configured to switch from the memory cell to a redundant memory cell associated with the memory cell using an interconnection gating signal.

### Claim 8 (depends on 1)

The electronic device of claim 1, wherein a redundant memory cell associated the memory cell includes a configuration memory bit for the memory cell.

### Claim 9 (depends on 1)

The electronic device of claim 1, wherein the electronic device comprises a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), coarse grained reconfigurable architecture (CGRA), central processing unit (CPU), graphics processing unit (GPU), hardware accelerator, or a combination thereof.

### Claim 10 (depends on 1)

The electronic device of claim 1, wherein the memory cell comprises at least one of 4 transistors, 6 transistors, 8 transistors, 10 transistors, 12 transistors, and a combination thereof.

### Claim 11 (depends on 1)

The electronic device of claim 1, wherein the single event effect is a single event transient (SET) or a single event upset (SEU).

### Claim 12 (depends on 1)

The electronic device of claim 1, wherein the sensor conditioner that includes at least one of a voltage divider, an inverter, and a buffer.

### Claim 13

A field-programmable gate array (FPGA) operable for single event effect mitigation, comprising:
a memory cell comprising:
a substrate;
a deep well coupled to the substrate;
a ground-coupled well coupled to the deep well;
an integrated particle sensor comprising one or more p-n junctions intentionally configured for actively detecting particle strikes, the integrated particle sensor coupled between:
the substrate and the deep well, and
the ground-coupled well and the deep well,
wherein the integrated particle sensor is operable to detect an ionizing particle generating the single event effect and output a corresponding detection signal; and
a sensor conditioner coupled to directly receive the detection signal from the integrated particle sensor, wherein the sensor conditioner that includes a current-to-voltage converter, an amplifier, and a pulse generator, and wherein the sensor conditioner is tuned to process the detection signal to generate a pulse and activate reconfiguration to a redundant memory cell when the single event effect occurs.

### Claim 14 (depends on 13)

The FPGA of claim 13, wherein the memory cell has a triple-quadruple well transistor design.

### Claim 15 (depends on 13)

The FPGA of claim 13, wherein a redundant memory cell associated with the memory cell is positioned at a threshold distance that prevents the ionizing particle from generating the single event effect in both the memory cell and the redundant memory cell.

### Claim 16 (depends on 13)

The FPGA of claim 13, wherein the memory cell comprises at least one of 4 transistors, 6 transistors, 8 transistors, 10 transistors, 12 transistors, and a combination thereof.

### Claim 17 (depends on 13)

The FPGA of claim 13, wherein the single event effect is a single event transient (SET) or a single event upset (SEU).

### Claim 18 (depends on 13)

The FPGA of claim 13, wherein the sensor conditioner includes at least one of a voltage divider, an inverter, and a buffer.