# US 12,112,819 B2 · Apparatus for determining memory cell data states

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- Number: US 12,112,819 B2
- Document ID: US12112819B2
- Status: Granted
- Kind: B2
- Application number: 18/376,198
- Filed: 2023-10-03
- Published: 2024-01-25
- Granted: 2024-10-08
- Earliest claimed: 2022-02-28
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Sheyang Ning; Lawrence Celso Miranda; Tomoko Ogura Iwasaki; Ting Luo; Luyen Vu
- Web page: https://patentgrep.com/patent/US12112819B2

## CPC

- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 7/1069: {I/O lines read out arrangements}
- G11C 7/1096: {Write circuits, e.g. I/O line write drivers}
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 29/12005: {comprising voltage or current generators}
- G11C 29/44: Indication or identification of errors, e.g. for repair
- G11C 29/4401: {for self repair}
- G11C 7/062: {Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs}
- G11C 7/067: {Single-ended amplifiers}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Apparatus might include an array of memory cells and a controller for access of the array of memory cells. The controller might be configured to cause the apparatus to apply a sense voltage level to a control gate of a memory cell of the array of memory cells, generate N determinations whether the memory cell is deemed to activate or deactivate while applying the sense voltage level, wherein N is an integer value greater than or equal to three, deem the memory cell to have a threshold voltage in a first range of threshold voltages lower than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell, and deem the memory cell to have a threshold voltage in a second range of threshold voltages higher than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell.

## Claims

### Claim 1

An apparatus, comprising:
an array of memory cells; and
a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to:
apply a sense voltage level to a control gate of a memory cell of the array of memory cells;
generate N determinations whether the memory cell is deemed to activate or deactivate while applying the sense voltage level, wherein N is an integer value greater than or equal to three;
deem the memory cell to have a threshold voltage in a first range of threshold voltages lower than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell; and
deem the memory cell to have a threshold voltage in a second range of threshold voltages higher than the sense voltage level in response to a majority of the N determinations indicating deactivation of the memory cell.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the controller being configured to cause the apparatus to generate N determinations whether the memory cell is deemed to activate or deactivate while applying the sense voltage level comprises the controller being configured to cause the apparatus to perform N sense operations on the memory cell.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the controller being configured to cause the apparatus to perform N sense operations on the memory cell comprises the controller being configured to cause the apparatus to perform N sense operations on the memory cell without discharging the control gate of the memory cell between sense operations of the N sense operations.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the controller being configured to cause the apparatus to generate N determinations whether the memory cell is deemed to activate or deactivate while applying the sense voltage level comprises the controller being configured to strobe a sense circuit N times, wherein the sense circuit has a sense node selectively connected to a data line that is selectively connected to the memory cell.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the controller being configured to strobe a sense circuit N times comprises the controller being configured to strobe a sense circuit N times without connecting the sense node to the data line between the strobes.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the controller being configured to cause the apparatus to deem the memory cell to have a threshold voltage in the first range of threshold voltages comprises the controller being configured to cause the apparatus to deem the memory cell to have a first data value.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the first data value consists of a single digit of data.

### Claim 8 (depends on 6)

The apparatus of claim 6, wherein the controller being configured to cause the apparatus to deem the memory cell to have a threshold voltage in the second range of threshold voltages comprises the controller being configured to cause the apparatus to deem the memory cell to have a second data value different than the first data value.

### Claim 9 (depends on 6)

The apparatus of claim 6, wherein the sense voltage level is a second sense voltage level, wherein the N determinations are a second N determinations, and wherein the controller is further configured to cause the apparatus to:
apply a first sense voltage level to the control gate of the memory cell prior to applying the second sense voltage level to the control gate of the memory cell, wherein the first sense voltage level is lower than the second sense voltage level;
generate a first N determinations whether the memory cell is deemed to activate or deactivate while applying the first sense voltage level;
deem the memory cell to have a second data value different than the first data value in response to a majority of the first N determinations indicating activation of the memory cell while applying the first sense voltage level or a majority of the second N determinations indicating deactivation of the memory cell while applying the second sense voltage level; and
deem the memory cell to have the first data value in response to a majority of the first N determinations indicating deactivation of the memory cell while applying the first sense voltage level and a majority of the second N determinations indicating activation of the memory cell while applying the second sense voltage level.

### Claim 10

An apparatus, comprising:
an array of memory cells; and
a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to:
sense a data state of a memory cell, of the array of memory cells, for N iterations to determine N instances of data, wherein N is an integer value greater than or equal to three, wherein each iteration of the N iterations corresponds to a respective instance of data of the N instances of data, and wherein the N instances of data each indicate a respective data value for the memory cell selected from a group consisting of a first data value, and a second data value different than the first data value; and
deem the data state of the memory cell to have the first data value in response to a majority of the N instances of data indicating the first data value for the memory cell.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the controller is further configured to cause the apparatus to deem the data state of the memory cell to have the second data value in response to a majority of the N instances of data indicating the second data value for the memory cell.

### Claim 12 (depends on 10)

The apparatus of claim 10, wherein N is an odd integer.

### Claim 13 (depends on 10)

The apparatus of claim 10, wherein the controller being configured to cause the apparatus to sense the data state of the memory cell for N iterations comprises the controller being configured to cause the apparatus to perform N sense operations on the memory cell.

### Claim 14 (depends on 13)

The apparatus of claim 13, wherein the controller being configured to cause the apparatus to perform N sense operations on the memory cell comprises the controller being configured to cause the apparatus to perform N sense operations on the memory cell without discharging a control gate of the memory cell between sense operations.

### Claim 15

An apparatus, comprising:
an array of memory cells; and
a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to:
apply a sense voltage level to a respective control gate of each memory cell of a plurality of memory cells of the array of memory cells; and
for each memory cell of the plurality of memory cells:
generate N determinations whether that memory cell is deemed to activate or deactivate while applying the sense voltage level, wherein N is an integer value greater than or equal to three;
deem that memory cell to have a threshold voltage in a first range of threshold voltages lower than the sense voltage level in response to a majority of the N determinations for that memory cell indicating activation of that memory cell; and
deem that memory cell to have a threshold voltage in a second range of threshold voltages higher than the sense voltage level in response to a majority of the N determinations for that memory cell indicating deactivation of that memory cell.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the controller being configured to cause the apparatus to generate the N determinations for each memory cell of the plurality of memory cells comprises the controller being configured to cause the apparatus to generate the N determinations for each memory cell of the plurality of memory cells in response to a prior read operation of the plurality of memory cells resulting in an uncorrectable number of errors.

### Claim 17 (depends on 15)

The apparatus of claim 15, wherein the controller being configured to cause the apparatus to deem any memory cell of the plurality of memory cells to have a threshold voltage in the first range of threshold voltages in response to a majority of the N determinations for that memory cell indicating activation of that memory cell comprises the controller being further configured to cause the apparatus to deem that memory cell to have a first data value, and wherein the controller being configured to cause the apparatus to deem that memory cell to have a threshold voltage in the second range of threshold voltages in response to a majority of the N determinations for that memory cell indicating deactivation of that memory cell comprises the controller being further configured to cause the apparatus to deem that memory cell to have a second data value different than the first data value.

### Claim 18 (depends on 15)

The apparatus of claim 15, wherein the controller is further configured to cause the apparatus to:
generate a combined set of data, wherein the combined set of data comprises a respective digit position for each memory cell of the plurality of memory cells, and wherein each digit position of the combined set of data has a data value equal to the data value its respective memory cell of the plurality of memory cells is deemed to have in response to a majority of its N determinations;
perform error checking on the combined set of data;
in response to an identification of no errors in the combined set of data, output the combined set of data; and
in response to an identification of a correctable number of errors in the combined set of data, perform error correction on the combined set of data and output a corrected version of the combined set of data.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein the sense voltage is a first sense voltage level, wherein the N determinations for each memory cell of the plurality of memory cells is a first N determinations for each memory cell of the plurality of memory cells, and wherein the controller, in response to an identification of an uncorrectable number of errors in the combined set of data, is further configured to cause the apparatus to:
apply a second sense voltage level to the respective control gate of each memory cell of the plurality of memory cells, wherein the second sense voltage level is different than the first sense voltage level; and
for each memory cell of the plurality of memory cells:
generate a second N determinations whether that memory cell is deemed to activate or deactivate while applying the second sense voltage level;
deem that memory cell to have a threshold voltage in the first range of threshold voltages in response to a majority of the second N determinations for that memory cell indicating activation of that memory cell; and
deem that memory cell to have a threshold voltage in the second range of threshold voltages in response to a majority of the second N determinations for that memory cell indicating deactivation of that memory cell.

### Claim 20 (depends on 18)

The apparatus of claim 18, wherein the controller, in response to an identification of an uncorrectable number of errors in the combined set of data, is further configured to cause the apparatus to indicate a failure condition.