# US 12,112,817 B2 · Test method, computer apparatus, and computer-readable storage medium

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- Number: US 12,112,817 B2
- Document ID: US12112817B2
- Status: Granted
- Kind: B2
- Application number: 17/827,997
- Filed: 2022-05-30
- Published: 2023-08-24
- Granted: 2024-10-08
- Earliest claimed: 2022-02-24
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Biao Song
- Web page: https://patentgrep.com/patent/US12112817B2

## CPC

- G11C 29/36: Data generation devices, e.g. data inverters
- G11C 29/50012: {of timing}
- G11C 29/08: Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C 29/12: Built-in arrangements for testing, e.g. built-in self testing [BIST] {or interconnection details}
- G11C 29/1201: {comprising I/O circuitry}
- G11C 29/12015: {comprising clock generation or timing circuitry}
- G11C 29/4401: {for self repair}
- G11C 29/50016: {of retention}
- G11C 29/56: External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C 2029/3602: {Pattern generator}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Embodiments relate to a test method, a computer apparatus, and a computer-readable storage medium. The test method includes: writing first data into a target memory cell; performing reverse writing on the target memory cell; reading second data stored in the target memory cell after the reverse writing; determining whether the second data are the same as the first data; and determining that write recovery time of the target memory cell fails when the second data are the same as the first data. The present disclosure can make an effective test of determining whether the write recovery time fails.

## Claims

### Claim 1

A test method comprising:
writing first data into a target memory cell;
performing reverse writing on the target memory cell;
reading second data stored in the target memory cell after the reverse writing;
determining whether the second data are the same as the first data; and
determining that write recovery time of the target memory cell fails when the second data are the same as the first data; and,
wherein after the determining that write recovery time of the target memory cell fails when the second data are the same as the first data, the test method further comprises:
detecting whether there is provided with an isolation layer between a bit line and a bit line contact hole structure of the target memory cell.

### Claim 2 (depends on 1)

The test method according to claim 1, wherein after the writing first data into the target memory cell and before the performing reverse writing on the target memory cell, the test method comprises:
setting CSL ON time less than preset time.

### Claim 3 (depends on 2)

The test method according to claim 2, wherein after the determining whether the second data are the same as the first data, the test method further comprises:
when the second data are different from the first data, setting the CSL ON time again to shorten the CSL ON time until the second data are the same as the first data, to obtain CSL ON time when the second data are the same as the first data.

### Claim 4 (depends on 1)

The test method according to claim 1, wherein
after the writing first data into the target memory cell and before the performing reverse writing on the target memory cell, the test method further comprises:
reading the first data stored in the target memory cell.

### Claim 5 (depends on 1)

The test method according to any one of claim 1, wherein before the writing first data into the target memory cell, the test method comprises:
setting a power supply voltage of the target memory cell.

### Claim 6 (depends on 1)

The test method according to claim 1, wherein while writing first data into the target memory cell, data opposite to the first data are written into all other memory cells positioned around and adjacent to the target memory cell.

### Claim 7 (depends on 6)

The test method according to claim 6, wherein the first data are represented by “1”, the data opposite to the first data being represented by “0”.

### Claim 8 (depends on 6)

The test method according to claim 6, wherein data are written into a target memory array in an X-fast manner, such that the first data are written into the target memory cell and the data opposite to the first data are written into all other memory cells in the target memory array.

### Claim 9 (depends on 8)

The test method according to claim 8, wherein a to-be-tested memory device comprises a plurality of memory banks, each of the plurality of memory banks comprising a plurality of memory arrays; and
before the data are written into the target memory array in the X-fast manner, the test method further comprises:
determining a target memory bank from the plurality of memory banks; and
determining the target memory array from the plurality of memory arrays of the target memory bank.

### Claim 10 (depends on 8)

The test method according to claim 8, wherein, before the data are written into the target memory array in the X-fast manner, the test method comprises:
writing “0” into all memory cells of a to-be-tested memory device.

### Claim 11 (depends on 10)

The test method according to claim 10, wherein after writing “0” into all memory cells of the to-be-tested memory device, the test method further comprises:
refreshing all the memory cells of the to-be-tested memory device.

### Claim 12 (depends on 10)

The test method according to claim 10, wherein before writing “0” into all memory cells of the to-be-tested memory device, the test method further comprises:
removing residual information for all the memory cells of the to-be-tested memory device, and initializing the to-be-tested memory device.

### Claim 13 (depends on 1)

A computer apparatus comprising a memory storing a computer program and a processor, the computer program is executable by the processor to implement a test method according to claim 1.

### Claim 14 (depends on 1)

A non-transitory computer-readable storage medium, storing a computer program thereon, the computer program is executable by a processor to implement a test method according to claim 1.

### Claim 15

A test method comprising:
writing first data into a target memory cell;
performing reverse writing on the target memory cell;
reading second data stored in the target memory cell after the reverse writing;
determining whether the second data are the same as the first data; and
determining that write recovery time of the target memory cell fails when the second data are the same as the first data;
wherein after the writing first data into the target memory cell and before the performing reverse writing on the target memory cell, the test method comprises:
setting CSL ON time less than preset time;
wherein after the determining whether the second data are the same as the first data, the test method further comprises:
when the second data are different from the first data, setting the CSL ON time again to shorten the CSL ON time until the second data are the same as the first data, to obtain CSL ON time when the second data are the same as the first data.

### Claim 16 (depends on 15)

A computer apparatus comprising a memory storing a computer program and a processor, the computer program is executable by the processor to implement a test method according to claim 15.

### Claim 17 (depends on 15)

A non-transitory computer-readable storage medium, storing a computer program thereon, the computer program is executable by a processor to implement a test method according to claim 15.