# US 12,112,811 B2 · Power leakage blocking in low-dropout regulator

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,112,811 B2
- Document ID: US12112811B2
- Status: Granted
- Kind: B2
- Application number: 18/242,397
- Filed: 2023-09-05
- Published: 2023-12-21
- Granted: 2024-10-08
- Earliest claimed: 2021-06-07
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Ruxin Wei
- Web page: https://patentgrep.com/patent/US12112811B2

## CPC

- G11C 16/30: Power supply circuits
- G05F 1/461: {using an operational amplifier as final control device}
- G05F 1/575: characterised by the feedback circuit
- G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

In certain aspects, a circuit includes an amplifier, a first transistor, a second transistor, a third transistor, a signal pair generation circuit, and a leakage track bias generator circuit connected to the signal pair generation circuit. A gate terminal of the first transistor is connected to an output of the amplifier, and a first terminal of the first transistor is connected to an input of the amplifier. A first terminal of the second transistor is connected to a second terminal of the first transistor. A first terminal of the third transistor is connected to the first terminal of the first transistor, and a second terminal of the third transistor is connected to a second terminal of the second transistor. The signal pair generation circuit is connected to a gate terminal of the second transistor and a gate terminal of the third transistor. The leakage track bias generator circuit includes a resistor, and a first terminal of the resistor is connected to the ground.

## Claims

### Claim 1

A circuit, comprising:
an amplifier;
a first transistor, wherein a gate terminal of the first transistor is connected to an output of the amplifier, and a first terminal of the first transistor is connected to an input of the amplifier;
a second transistor, wherein a first terminal of the second transistor is connected to a second terminal of the first transistor;
a third transistor, wherein a first terminal of the third transistor is connected to the first terminal of the first transistor, and a second terminal of the third transistor is connected to a second terminal of the second transistor;
a signal pair generation circuit connected to a gate terminal of the second transistor and a gate terminal of the third transistor; and
a leakage track bias generator circuit connected to the signal pair generation circuit, wherein the leakage track bias generator circuit comprises a resistor, and a first terminal of the resistor is connected to a reference voltage.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein the leakage track bias generator circuit comprises a first input and a second input, and the leakage track bias generator circuit is configured to output a control voltage to the signal pair generation circuit based on a voltage of the first input and a voltage of the second input.

### Claim 3 (depends on 2)

The circuit of claim 2, wherein the signal pair generation circuit is configured to output a first signal to the gate terminal of the second transistor and a second signal to the gate terminal of the third transistor based on the control voltage.

### Claim 4 (depends on 1)

The circuit of claim 1, wherein a bulk of the first transistor, a bulk of the second transistor, and a bulk of the third transistor are connected together.

### Claim 5 (depends on 1)

The circuit of claim 1, wherein
the leakage track bias generator circuit further comprises four p-channel metal-oxide-semiconductor (PMOS) transistors and two n-channel metal-oxide-semiconductor (NMOS) transistors;
respective sources of the two NMOS transistors are connected to the reference voltage; and
respective gates of the two NMOS transistors are connected to each other.

### Claim 6 (depends on 5)

The circuit of claim 5, wherein bulks of the four PMOS transistors are connected together.

### Claim 7 (depends on 5)

The circuit of claim 5, wherein gate terminals of the four PMOS transistors are connected together.

### Claim 8 (depends on 5)

The circuit of claim 5, wherein
the two NMOS transistors are connected to respective terminals of two of the four PMOS transistors comprising a first PMOS transistor and a second PMOS transistor; and
a first terminal of the first PMOS transistor is connected to a first input, and a first terminal of the second PMOS transistor is connected to a second input.

### Claim 9 (depends on 8)

The circuit of claim 8, wherein
the four PMOS transistors further comprise a third PMOS transistor and a fourth PMOS transistor; and
first terminals of the third PMOS transistor and the first PMOS transistor are connected together, and first terminals of the fourth PMOS transistor and the second PMOS transistor are connected together.

### Claim 10 (depends on 1)

The circuit of claim 1, wherein a resistance of the resistor is related to physical characteristics of the first transistor.

### Claim 11 (depends on 9)

The circuit of claim 9, wherein a second terminal of the resistor is connected to a second terminal of the third PMOS transistor and a second terminal of the fourth PMOS transistor.

### Claim 12 (depends on 3)

The circuit of claim 3, wherein
when a first voltage of the first input is greater than a second voltage of the second input, the first signal and the second signal are configured to turn the second transistor on and the third transistor off, and
when the first voltage is lower than the second voltage, the first signal and the second signal are configured to turn the second transistor off and the third transistor on.

### Claim 13 (depends on 1)

The circuit of claim 1, wherein
the signal pair generation circuit comprises four transistors comprising a fifth PMOS transistor, a sixth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;
sources of the fifth PMOS transistor and the sixth PMOS transistor are connected to one another, and sources of the third NMOS transistor and the fourth NMOS transistor are connected to the reference voltage; and
a drain of the fifth PMOS transistor is connected to a drain of the third NMOS transistor, and a drain of the sixth PMOS transistor is connected to a drain of the fourth NMOS transistor.

### Claim 14 (depends on 13)

The circuit of claim 13, wherein
a first output of the signal pair generation circuit is taken from a node between the drain of the sixth PMOS transistor and the drain of the fourth NMOS transistor, and the first output is connected to the gate terminal of the third transistor; and
a second output of the signal pair generation circuit is taken from a gate of the fourth NMOS transistor, and the second output is connected to the gate terminal of the second transistor.

### Claim 15

A circuit, comprising:
a low-dropout regulator comprising a first transistor, wherein the low-dropout regulator is configured to output a second voltage based on a first voltage;
a pair of transistors comprising a second transistor and a third transistor, wherein respective bulks of the pair of transistors are connected to a bulk of the first transistor; and
a control circuit connected to gates of the pair of transistors, wherein the control circuit is configured to output signals to the gates of the pair of transistors, the control circuit comprises a resistor, and a first terminal of the resistor is connected to a reference voltage.

### Claim 16 (depends on 15)

The circuit of claim 15, wherein
the control circuit comprises a signal pair generation circuit configured to output signals to the gates of the pair of transistors based on a control voltage; and
the control voltage is related to the first voltage and the second voltage.

### Claim 17 (depends on 16)

The circuit of claim 16, wherein
the control circuit further comprises a leakage track bias generator circuit connected to the signal pair generation circuit; and
the leakage track bias generator circuit is configured to output the control voltage to the signal pair generation circuit based on the first voltage and the second voltage.

### Claim 18 (depends on 15)

The circuit of claim 15, wherein
when the first voltage is greater than the second voltage, the signals are configured to turn the second transistor on and the third transistor off; and
when the first voltage is lower than the second voltage, the signals are configured to turn the second transistor off and the third transistor on.

### Claim 19 (depends on 15)

The circuit of claim 15, wherein the second transistor and the third transistor are connected in series.

### Claim 20

A memory device, comprising:
a memory array for storing data; and
a peripheral circuit coupled to the memory array and comprising a voltage generation circuit, the voltage generation circuit comprising:
an amplifier;
a first transistor; wherein a gate terminal of the first transistor is connected to an output of the amplifier, and a first terminal of the first transistor is connected to an input of the amplifier;
a second transistor, wherein a first terminal of the second transistor connected to a second terminal of the first transistor;
a third transistor, wherein a first terminal of the third transistor is connected to the first terminal of the second transistor, and a second terminal of the third transistor is connected to a second terminal of the first transistor;
a signal pair generation circuit connected to a gate terminal of the second transistor and a gate terminal of the third transistor; and
a leakage track bias generator circuit connected to the signal pair generation circuit, wherein the leakage track bias generator circuit comprises a resistor, and a first terminal of the resistor is connected to a reference voltage.