# US 12,112,810 B2 · Non-volatile semiconductor storage device

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- Number: US 12,112,810 B2
- Document ID: US12112810B2
- Status: Granted
- Kind: B2
- Application number: 18/296,430
- Filed: 2023-04-06
- Published: 2023-08-17
- Granted: 2024-10-08
- Earliest claimed: 2011-12-09
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Naoki Matsunaga
- Web page: https://patentgrep.com/patent/US12112810B2

## CPC

- G11C 16/26: Sensing or reading circuits; Data output circuits
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/064: {Management of blocks}
- G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/04: using variable threshold transistors, e.g. FAMOS
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/06: Auxiliary circuits, e.g. for writing into memory
- G11C 16/3404: {Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells}
- G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles}
- G11C 16/3495: {Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.

## Claims

### Claim 1

An information processing apparatus connectable to a memory system, the information processing apparatus comprising:
a display device; and
a processor configured to transmit a read request to the memory system,
wherein the memory system includes:
a nonvolatile memory; and
a controller circuit configured to:
receive the read request from the information processing apparatus;
on receiving the read request, perform a read processing until the read processing succeeds, the read processing including a first read operation and one or more second read operation, the first read operation including reading data from the nonvolatile memory with a first parameter, the second read operation including reading the data from the nonvolatile memory with a second parameter that is different from the first parameter; and
if a number of the first and second read operations exceeds a first threshold, transmit, to the information processing apparatus, information about a life of the nonvolatile memory based on the number of the first and second read operations,
wherein the processor is further configured to:
receive, from the memory system, the information about the life of the nonvolatile memory; and
cause the display device to display the life of the nonvolatile memory.

### Claim 2 (depends on 1)

The information processing apparatus according to claim 1 wherein
the controller of the memory system is further configured to:
compare the number of the first and second read operations with the first threshold;
determine a degree of deterioration of the nonvolatile memory in accordance with a result of the comparing; and
transmit the degree of deterioration of the nonvolatile memory to the information processing apparatus, and
wherein the processor is further configured to:
receive, from the memory system, the degree of deterioration of the nonvolatile memory;
and
cause the display device to display the degree of deterioration of the nonvolatile memory.

### Claim 3 (depends on 1)

The information processing apparatus according to claim 1 wherein
the nonvolatile memory includes a plurality of memory cells,
the controller of the memory system is further configured to:
monitor a number of bit errors in data in the plurality of memory cells in performing the first and second read operations;
determine a degree of deterioration of the nonvolatile memory in accordance with a result of the monitoring; and
transmit the degree of deterioration of the nonvolatile memory to the information processing apparatus, and
wherein the processor is further configured to:
receive, from the memory system, the degree of deterioration of the nonvolatile memory;
and
cause the display device to display the degree of deterioration of the nonvolatile memory.

### Claim 4 (depends on 3)

The information processing apparatus according to claim 3 wherein
the controller of the memory system is further configured to:
if the number of bit errors exceeds a second threshold, transmit, to the information processing apparatus, information about the life of the nonvolatile memory based on the number of bit errors,
wherein the processor is further configured to:
receive the information about the life of the nonvolatile memory based on the number of bit errors; and
cause the display device to display the life of the nonvolatile memory.

### Claim 5 (depends on 1)

The information processing apparatus according to claim 1, wherein
the nonvolatile memory includes a plurality of memory cells, and each of the plurality of memory cells is configured to store two or more than two bits of data.

### Claim 6 (depends on 2)

The information processing apparatus according to claim 2, wherein
the nonvolatile memory is a NAND type flash memory.

### Claim 7 (depends on 1)

The information processing apparatus according to claim 1, wherein
the nonvolatile memory includes a plurality of blocks, the plurality of blocks including a first block,
the controller of the memory system is further configured to:
if a number of the first and second read operations of the first block exceeds the first threshold, transmit, to the information processing apparatus, information about the life of the nonvolatile memory and identifier of the first block based on the number of the first and second read operations of the first block,
wherein the processor is further configured to:
receive the information about the life of the nonvolatile memory and identifier of the first block; and
cause the display device to display the life of the nonvolatile memory and the identifier of the first block.