# US 12,112,809 B2 · Method and apparatus for reading data stored in flash memory by referring to binary digit distribution characteristics of bit sequences read from flash memory

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- Number: US 12,112,809 B2
- Document ID: US12112809B2
- Status: Granted
- Kind: B2
- Application number: 18/219,083
- Filed: 2023-07-06
- Published: 2023-11-02
- Granted: 2024-10-08
- Earliest claimed: 2010-12-07
- Assignees: Silicon Motion, Inc.
- Applicants: Silicon Motion, Inc.
- Inventors: Tsung-Chieh Yang
- Web page: https://patentgrep.com/patent/US12112809B2

## CPC

- G11C 16/26: Sensing or reading circuits; Data output circuits
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/064: {Management of blocks}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G06F 11/1072: {in multilevel memories}
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- H03M 13/152: {Bose-Chaudhuri-Hocquenghem [BCH] codes}
- G11C 16/0475: {comprising two or more independent storage sites which store independent data}
- G11C 2211/5644: Multilevel memory comprising counting devices
- G11C 2211/5648: Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

## Claims

### Claim 1

A memory controller for reading data stored in a flash memory,
wherein the memory controller is configured to perform the steps of:
reading a plurality of memory cells of the flash memory by using a plurality of control gate voltages to obtain a plurality of bit sequences from the flash memory;
referring to the plurality of bit sequences to determine numbers of memory cells whose threshold voltages are located between a first control gate voltage and a second control gate voltage of the plurality of control gate voltages, to generate a first value;
referring to the plurality of bit sequences to determine numbers of memory cells whose threshold voltages are located between a third control gate voltage and a fourth control gate voltage of the plurality of control gate voltages, to generate a second value; and
updating at least one of the plurality of control gate voltages according to the first value and the second value.

### Claim 2 (depends on 1)

The memory controller of claim 1, wherein the first control gate voltage is lower than the second control gate voltage, the second control gate voltage is lower than the third control gate voltage, and the third control gate voltage is lower than the fourth control gate voltage.

### Claim 3 (depends on 2)

The memory controller of claim 2, wherein the first control gate voltage and the second control gate voltage are two adjacent control gate voltages, and the third control gate voltage and the fourth control gate voltage are two adjacent control gate voltages.

### Claim 4

A method for reading data stored in a flash memory, comprising:
reading a plurality of memory cells of the flash memory by using a plurality of control gate voltages to obtain a plurality of bit sequences from the flash memory;
referring to the plurality of bit sequences to determine numbers of memory cells whose threshold voltages are located between a first control gate voltage and a second control gate voltage of the plurality of control gate voltages, to generate a first value;
referring to the plurality of bit sequences to determine numbers of memory cells whose threshold voltages are located between a third control gate voltage and a fourth control gate voltage of the plurality of control gate voltages, to generate a second value; and
updating at least one of the plurality of control gate voltages according to the first value and the second value.

### Claim 5 (depends on 4)

The method of claim 4, wherein the first control gate voltage is lower than the second control gate voltage, the second control gate voltage is lower than the third control gate voltage, and the third control gate voltage is lower than the fourth control gate voltage.

### Claim 6 (depends on 5)

The method of claim 5, wherein the first control gate voltage and the second control gate voltage are two adjacent control gate voltages, and the third control gate voltage and the fourth control gate voltage are two adjacent control gate voltages.

### Claim 7

An electronic device, comprising:
a flash memory; and
a flash memory controller, configured to perform the steps of:
reading a plurality of memory cells of the flash memory by using a plurality of control gate voltages to obtain a plurality of bit sequences from the flash memory;
referring to the plurality of bit sequences to determine numbers of memory cells whose threshold voltages are located between a first control gate voltage and a second control gate voltage of the plurality of control gate voltages, to generate a first value;
referring to the plurality of bit sequences to determine numbers of memory cells whose threshold voltages are located between a third control gate voltage and a fourth control gate voltage of the plurality of control gate voltages, to generate a second value; and
updating at least one of the plurality of control gate voltages according to the first value and the second value.

### Claim 8 (depends on 7)

The electronic device of claim 7, wherein the first control gate voltage is lower than the second control gate voltage, the second control gate voltage is lower than the third control gate voltage, and the third control gate voltage is lower than the fourth control gate voltage.

### Claim 9 (depends on 8)

The electronic device of claim 8, wherein the first control gate voltage and the second control gate voltage are two adjacent control gate voltages, and the third control gate voltage and the fourth control gate voltage are two adjacent control gate voltages.