# US 12,112,802 B2 · Memory device, the operation method thereof and memory system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,112,802 B2 - Document ID: US12112802B2 - Status: Granted - Kind: B2 - Application number: 17/974,271 - Filed: 2022-10-26 - Published: 2024-01-25 - Granted: 2024-10-08 - Earliest claimed: 2022-07-21 - Assignees: Yangtze Memory Technologies Co., Ltd. - Applicants: Yangtze Memory Technologies Co., Ltd. - Inventors: Zhihong Li; Jing Wei; Masao Kuriyama - Web page: https://patentgrep.com/patent/US12112802B2 ## CPC - G11C 16/0433: {comprising cells containing a single floating gate transistor and one or more separate select transistors} - G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/10: Programming or data input circuits - G11C 16/102: {External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators} - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/30: Power supply circuits - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/32: Timing circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract The present disclosure provides a memory device comprising a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array includes a plurality of memory planes; the peripheral circuit includes a plurality of selected voltage selection circuits corresponding to the plurality of memory planes; a plurality of global word line voltage selection circuits respectively corresponding to each memory plane, and a plurality of local word line voltage selection circuits respectively corresponding to each memory plane. The plurality of selected voltage selection circuits are configured to select a voltage from a plurality of selected voltages to output to the global word line voltage selection circuits; the global word line voltage selection circuits are configured to select a voltage from unselected voltages and the voltage output from the plurality of selected voltage selection circuits to output to the local word line voltage selection circuits. ## Claims ### Claim 1 A memory device, comprising a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array comprises a plurality of memory planes; the peripheral circuit comprises a plurality of selected voltage selection circuits corresponding to the plurality of memory planes, a plurality of global word line voltage selection circuits respectively corresponding to each memory plane, and a plurality of local word line voltage selection circuits respectively corresponding to each memory plane; the plurality of selected voltage selection circuits are configured to select a voltage from a plurality of selected voltages to output to the global word line voltage selection circuits; the global word line voltage selection circuits are configured to select a voltage from unselected voltages and the voltage output from the plurality of selected voltage selection circuits to output to the local word line voltage selection circuits; during a program operation, the plurality of memory planes share the plurality of selected voltage selection circuits; and during a read operation, each memory plane uses a part of the plurality of selected voltage selection circuits respectively to perform voltage selection. ### Claim 2 (depends on 1) The memory device according to claim 1, wherein during the program operation, a number of the selected voltages corresponding to the plurality of memory planes is a, and a number of the selected voltage selection circuits corresponding to the plurality of memory planes is at least a; during the read operation, a number of the selected voltages corresponding to each memory plane is b, and a number of the selected voltage selection circuits corresponding to each memory plane is at least b; and a number of the memory planes is c, and a relationship among a, b, and c is: a≥b*c; wherein both a and b are positive integers greater than 0, and c is a positive integer greater than 1. ### Claim 3 (depends on 2) The memory device according to claim 2, wherein the peripheral circuit further comprises a plurality of global word lines corresponding to the global word line voltage selection circuits one-to-one; during the program operation, the number of the selected voltage selection circuits corresponding to the plurality of memory planes is a, and adjacent a global word lines on each memory plane correspond to different selected voltage selection circuits; and during the read operation, the global word lines on different memory planes correspond to different selected voltage selection circuits, the number of the selected voltage selection circuits corresponding to each memory plane is b, and adjacent b global word lines on each memory plane correspond to different selected voltage selection circuits. ### Claim 4 (depends on 1) The memory device according to claim 1, wherein the peripheral circuit further comprises a plurality of unselected voltage selection circuits corresponding to the plurality of memory planes; each unselected voltage selection circuit corresponds to the plurality of local word line voltage selection circuits on one memory plane, each local word line voltage selection circuit corresponds to one unselected voltage selection circuit; each of the plurality of unselected voltage selection circuits is configured to select a voltage from at least one unselected voltage to output to the local word line voltage selection circuits; during the program operation, the plurality of memory planes share the plurality of unselected voltage selection circuits; and during the read operation, each memory plane uses a part of the plurality of unselected voltage selection circuits respectively to perform voltage selection. ### Claim 5 (depends on 4) The memory device according to claim 4, wherein during the program operation, a number of the unselected voltages corresponding to the plurality of memory planes is d, and a number of the unselected voltage selection circuits corresponding to the plurality of memory planes is at least d; during the read operation, a number of the unselected voltages corresponding to each memory plane is e, and a number of the unselected voltage selection circuits corresponding to each memory plane is at least e; and a number of the memory planes is c, and a relationship among c, d, and e is: d≥e*c; wherein both d and e are positive integers greater than 0, and c is a positive integer greater than 1. ### Claim 6 (depends on 4) The memory device according to claim 4, wherein each of the memory planes comprises a plurality of word lines; the peripheral circuit further comprises a plurality of global word lines corresponding to the global word line voltage selection circuits one-to-one, and a plurality of local word lines corresponding to the local word line voltage selection circuits one-to-one, wherein each of the global word lines corresponds to the plurality of local word lines; each local word line corresponds to one global word line, and each local word line corresponds to one word line; the global word line voltage selection circuits output the voltage to the local word line voltage selection circuits through the global word lines; and the local word line voltage selection circuits output the voltage to corresponding word lines through the local word lines. ### Claim 7 (depends on 4) The memory device according to claim 4, wherein the selected voltage selection circuits, the global word line voltage selection circuits, the local word line voltage selection circuits, and the unselected voltage selection circuits all comprise a multiplexer. ### Claim 8 A memory system, comprising one or more memory devices and a memory controller coupled to and configured to control the one or more memory devices, wherein each of the memory devices comprises a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array comprises a plurality of memory planes; the peripheral circuit comprises a plurality of selected voltage selection circuits corresponding to the plurality of memory planes, a plurality of global word line voltage selection circuits respectively corresponding to each memory plane, and a plurality of local word line voltage selection circuits respectively corresponding to each memory plane; the plurality of selected voltage selection circuits are configured to select a voltage from a plurality of selected voltages to output to the global word line voltage selection circuits; the global word line voltage selection circuits are configured to select a voltage from unselected voltages and the voltage output from the plurality of selected voltage selection circuits to output to the local word line voltage selection circuits; during a program operation, the plurality of memory planes share the plurality of selected voltage selection circuits; and during a read operation, each memory plane uses a part of the plurality of selected voltage selection circuits respectively to perform voltage selection. ### Claim 9 (depends on 8) The memory system according to claim 8, wherein during the program operation, a number of the selected voltages corresponding to the plurality of memory planes is a, and a number of the selected voltage selection circuits corresponding to the plurality of memory planes is at least a; during the read operation, a number of the selected voltages corresponding to each memory plane is b, and a number of the selected voltage selection circuits corresponding to each memory plane is at least b; and a number of the memory planes is c, and a relationship among a, b, and c is: a≥b*c; wherein both a and b are positive integers greater than 0, and c is a positive integer greater than 1. ### Claim 10 (depends on 9) The memory system according to claim 9, wherein the peripheral circuit further comprises a plurality of global word lines corresponding to the global word line voltage selection circuits one-to-one; during the program operation, the number of the selected voltage selection circuits corresponding to the plurality of memory planes is a, and adjacent a global word lines on each memory plane correspond to different selected voltage selection circuits; and during the read operation, the global word lines on different memory planes correspond to different selected voltage selection circuits, the number of the selected voltage selection circuits corresponding to each memory plane is b, and adjacent b global word lines on each memory plane correspond to different selected voltage selection circuits. ### Claim 11 (depends on 8) The memory system according to claim 8, wherein the peripheral circuit further comprises a plurality of unselected voltage selection circuits corresponding to the plurality of memory planes; each unselected voltage selection circuit corresponds to the plurality of local word line voltage selection circuits on one memory plane, each local word line voltage selection circuit corresponds to one unselected voltage selection circuit; each of the plurality of unselected voltage selection circuits is configured to select a voltage from at least one unselected voltage to output to the local word line voltage selection circuits; during the program operation, the plurality of memory planes share the plurality of unselected voltage selection circuits; and during the read operation, each memory plane uses a part of the plurality of unselected voltage selection circuits respectively to perform voltage selection. ### Claim 12 (depends on 11) The memory system according to claim 11, wherein During the program operation, a number of the unselected voltages corresponding to the plurality of memory planes is 61, and a number of the unselected voltage selection circuits corresponding to the plurality of memory planes is at least ci; during the read operation, a number of the unselected voltages corresponding to each memory plane is e, and a number of the unselected voltage selection circuits corresponding to each memory plane is at least e; and a number of the memory planes is c, and a relationship among c, d, and e is: d≥e*c: wherein both d and e are positive integers greater than 0, and c is a positive integer greater than 1. ### Claim 13 (depends on 11) The memory system according to claim 11, wherein each of the memory planes comprises a plurality of word lines; the peripheral circuit further comprises a plurality of global word lines corresponding to the global word line voltage selection circuits one-to-one, and a plurality of local word lines corresponding to the local word line voltage selection circuits one-to-one, wherein each of the global word lines corresponds to the plurality of local word lines; each local word line corresponds to one global word line, and each local word line corresponds to one word line; the global word line voltage selection circuits output the voltage to the local word line voltage selection circuits through the global word lines; and the local word line voltage selection circuits output the voltage to corresponding word lines through the local word lines. ### Claim 14 (depends on 11) The memory system according to claim 11, wherein the selected voltage selection circuits, the global word line voltage selection circuits, the local word line voltage selection circuits, and the unselected voltage selection circuits all comprise a multiplexer. ### Claim 15 (depends on 8) The memory system according to claim 8, wherein the memory system comprises a memory card or a solid state hard disk. ### Claim 16 A method for operating a memory device, wherein the memory device comprises a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array comprises a plurality of memory planes; the peripheral circuit comprises a plurality of selected voltage selection circuits corresponding to the plurality of memory planes, a plurality of global word line voltage selection circuits respectively corresponding to each memory plane; and a plurality of local word line voltage selection circuits respectively corresponding to each memory plane; the plurality of selected voltage selection circuits are configured to select a voltage from a plurality of selected voltages to output to the global word line voltage selection circuits; the global word line voltage selection circuits are configured to select a voltage from unselected voltages and the voltage output from the plurality of selected voltage selection circuits to output to the local word line voltage selection circuits; the method comprises: receiving a first instruction, wherein the first instruction is configured to simultaneously perform a program operation on the plurality of memory planes; applying a plurality of different voltages output by the plurality of selected voltage selection circuits to each memory plane in response to the first instruction; receiving a second instruction, wherein the second instruction is configured to perform a read operation on the plurality of memory planes; and applying a part of the plurality of different voltages output by the plurality of selected voltage selection circuits respectively to different memory planes in response to the second instruction. ### Claim 17 (depends on 16) The method according to claim 16, wherein during the program operation performed on the plurality of memory planes simultaneously, a number of the selected voltages corresponding to the plurality of memory planes is a, and a number of the selected voltage selection circuits corresponding to the plurality of memory planes is at least a; during the read operation performed on the plurality of memory planes, a number of the selected voltages corresponding to each memory plane is b, and a number of the selected voltage selection circuits corresponding to each memory plane is at least b; and a number of the memory planes is c, and a relationship among a, b, and c is: a≥b*c; wherein both a and b are positive integers greater than 0, and c is a positive integer greater than 1. ### Claim 18 (depends on 17) The method according to claim 17, wherein the peripheral circuit further comprises a plurality of global word lines corresponding to the global word line voltage selection circuits one-to-one; during the program operation performed on the plurality of memory planes simultaneously, the number of the selected voltage selection circuits corresponding to the plurality of memory planes is a, and adjacent a global word lines on each memory plane correspond to different selected voltage selection circuits; and during the read operation performed on the plurality of memory planes, the global word lines on different memory planes correspond to different selected voltage selection circuits, the number of the selected voltage selection circuits corresponding to each memory plane is b, and adjacent b global word lines on each memory plane correspond to different selected voltage selection circuits. ### Claim 19 (depends on 16) The method according to claim 16, wherein the peripheral circuit further comprises a plurality of unselected voltage selection circuits corresponding to the plurality of memory planes; each unselected voltage selection circuit corresponds to the plurality of local word line voltage selection circuits on one memory plane, each local word line voltage selection circuit corresponds to one unselected voltage selection circuit; each of the plurality of unselected voltage selection circuits is configured to select a voltage from at least one unselected voltage to output to the local word line voltage selection circuits; the method further comprises: applying a plurality of different voltages output by the plurality of unselected voltage selection circuits to each memory plane in response to the first instruction; and applying a part of the plurality of different voltages output by the plurality of unselected voltage selection circuits respectively to different memory planes in response to the second instruction. ### Claim 20 (depends on 19) The method according to claim 19, wherein during the program operation, a number of the unselected voltages corresponding to the plurality of memory planes is d, and a number of the unselected voltage selection circuits corresponding to the plurality of memory planes is at least d; during the read operation, a number of the unselected voltages corresponding to each memory plane is e, and a number of the unselected voltage selection circuits corresponding to each memory plane is at least e; and a number of the memory planes is c, and a relationship among c, d and, e is: d≥e*c; wherein both d and e are positive integers greater than 0, and c is a positive integer greater than 1.