# US 12,112,801 B2 · Forward looking algorithm for vertical integrated cross-point array memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,112,801 B2 - Document ID: US12112801B2 - Status: Granted - Kind: B2 - Application number: 17/897,021 - Filed: 2022-08-26 - Published: 2024-02-29 - Granted: 2024-10-08 - Earliest claimed: 2022-08-26 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Ferdinando Bedeschi - Web page: https://patentgrep.com/patent/US12112801B2 ## CPC - G11C 13/0035: {Evaluating degradation, retention or wearout, e.g. by counting writing cycles} - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 13/004: {Reading or sensing circuits or methods} - G11C 13/0061: {Timing circuits or methods} - G11C 2013/0052: {Read process characterized by the shape, e.g. form, length, amplitude of the read pulse} - G11C 2013/0057: {Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Systems and methods for reading a first and second plurality of memory cells include applying a first ramping voltage with a first increment for each ramping step to read the first plurality of cells, counting, among the first plurality of cells at each ramping step, a first number of logic 1 cells, comparing the first number with a threshold at each ramping step of the first ramping voltage, determining a first voltage reached by the first ramping voltage, at the first voltage the first number becoming equal to or higher than the threshold for the first time, applying a second voltage lower than the first voltage to read the second plurality of cells, and applying a second ramping voltage ramping up from the second voltage with a second predetermined increment lower than the first predetermined increment for each ramping step to read the second plurality of cells. ## Claims ### Claim 1 A method for reading a memory array having a first and second plurality of cells, the method comprising: applying a first ramping voltage with a first predetermined increment for each of a plurality of ramping steps of the first ramping voltage to read the first plurality of cells; counting, among the first plurality of cells at each ramping step of the first ramping voltage, a first number of cells at a logic 1 state; comparing the first number with a first predetermined threshold at each ramping step of the first ramping voltage; determining a first voltage reached by the first ramping voltage, at the first voltage the first number becoming equal to or higher than the first predetermined threshold; applying a second voltage to read the second plurality of cells, the second voltage being lower than the first voltage by a first predetermined amount; and applying a second ramping voltage ramping up from the second voltage with a second predetermined increment for each ramping step to read the second plurality of cells, the second predetermined increment being lower than the first predetermined increment by a second predetermined amount. ### Claim 2 (depends on 1) The method of claim 1, wherein the first plurality of cells are known pattern cells and the second plurality of cells are data cells. ### Claim 3 (depends on 1) The method of claim 1, further comprising applying a third ramping voltage ramping up to the second voltage to read the second plurality of cells, the third ramping voltage using the first predetermined increment for each ramping step. ### Claim 4 (depends on 3) The method of claim 3, further comprising: counting, among the second plurality of cells at each ramping step of the third ramping voltage, a second number of cells at a logic 1 state; comparing the second number with a second predetermined threshold; and determining the first voltage when both a first and second condition are satisfied for a first time, the first condition being the first number becoming equal to or higher than the first predetermined threshold, and the second condition being the second number becoming higher than the second predetermined threshold. ### Claim 5 (depends on 1) The method of claim 1, further comprising: counting, among the second plurality of cells at a first step of the second ramping voltage, a third number of cells at the logic 1 state; counting, among the second plurality of cells at a second step of the second ramping voltage, a fourth number of cells at the logic 1 state, the second step immediately following the first step; calculating a difference between the third number and the fourth number; and stopping the second ramping voltage when an absolute value of the difference is smaller than a third predetermined threshold. ### Claim 6 (depends on 5) The method of claim 5, further comprising providing the stopping voltage of the second ramping voltage to a sense amplifier. ### Claim 7 (depends on 5) The method of claim 5, further comprising: adding a pulsed voltage to the stopping voltage of the second ramping voltage to read the second plurality of cells; and counting, among the second plurality of cells, a fifth number of cells at the logic 1 state. ### Claim 8 (depends on 1) The method of claim 1, further comprising: reading a third plurality of cells located adjacent the first and second plurality of cells; and stopping the first ramping voltage when a number of cells at a logic 0 state among the third plurality of cells exceeds a fourth predetermined threshold. ### Claim 9 (depends on 8) The method of claim 8, wherein the third plurality of cells reflects page erase status. ### Claim 10 (depends on 1) The method of claim 1, further comprising stopping the second ramping voltage when a predetermined number of steps in the second ramping voltage is reached. ### Claim 11 A memory device comprising: a memory array having a first and second plurality of cells; a controller configured to: apply a first ramping voltage with a first predetermined increment for each of a plurality of ramping steps of the first ramping voltage to read the first plurality of cells; count, among the first plurality of cells at each ramping step of the first ramping voltage, a first number of cells at a logic 1 state; compare the first number with a first predetermined threshold at each ramping step of the first ramping voltage; determine a first voltage reached by the first ramping voltage, at the first voltage the first number becoming equal to or higher than the first predetermined threshold; apply a second voltage to read the second plurality of cells, the second voltage being lower than the first voltage by a first predetermined amount; and apply a second ramping voltage ramping up from the second voltage with a second predetermined increment for each ramping step to read the second plurality of cells, the second predetermined increment being lower than the first predetermined increment by a second predetermined amount. ### Claim 12 (depends on 11) The memory device of claim 11, wherein the first plurality of cells are known pattern cells and the second plurality of cells are data cells. ### Claim 13 (depends on 11) The memory device of claim 11, wherein the controller is further configured to apply a third ramping voltage ramping up to the second voltage to read the second plurality of cells, the third ramping voltage using the first predetermined increment for each ramping step. ### Claim 14 (depends on 13) The memory device of claim 13, wherein the controller is further configured to: count, among the second plurality of cells at each ramping step of the third ramping voltage, a second number of cells at a logic 1 state; compare the second number with a second predetermined threshold at each ramping step; and determine the first voltage when both a first and second condition are satisfied for a first time, the first condition being the first number becoming equal to or higher than the first predetermined threshold, and the second condition being the second number becoming higher than the second predetermined threshold. ### Claim 15 (depends on 11) The memory device of claim 11, wherein the controller is further configured to: count, among the second plurality of cells at a first step of the second ramping voltage, a third number of cells at the logic 1 state; count, among the second plurality of cells at a second step of the second ramping voltage, a fourth number of cells at the logic 1 state, the second step following the first step; calculate a difference between the third number and the fourth number; and stop the second ramping voltage when an absolute value of the difference is smaller than a third predetermined threshold. ### Claim 16 (depends on 15) The memory device of claim 15, wherein the controller is further configured to: add a pulsed voltage to the stopping voltage of the second ramping voltage to read the second plurality of cells; and count, among the second plurality of cells, a fifth number of cells at the logic 1 state. ### Claim 17 (depends on 11) The memory device of claim 11, the controller is further configured to: read a third plurality of cells located adjacent the first and second plurality of cells; and stop the first ramping voltage when a number of cells at a logic 0 state among the third plurality of cells exceeds a fourth predetermined threshold. ### Claim 18 (depends on 17) The memory device of claim 17, wherein the third plurality of cells reflects page erase status. ### Claim 19 (depends on 11) The memory device of claim 11, wherein the controller is further configured to stop the second ramping voltage when a predetermined number of steps in the second ramping voltage is reached. ### Claim 20 A method for reading a memory array, the method comprising: simultaneously applying a first voltage and second voltage to read a first and second plurality of memory cells, respectively, the first voltage being higher than the second voltage by a first predetermined amount, the first plurality of memory cells having a known pattern; counting a first number of cells turned to a logic 1 state in the first plurality of memory cells; and subsequently applying a third voltage to read the second plurality of memory cells in response to the counting, wherein the third voltage is higher than the first voltage by either a second predetermined amount or a third predetermined amount lower than the second predetermined amount, wherein the second predetermined amount is chosen when the first number is lower than a first predetermined threshold, and the third predetermined amount is chosen when the first number is equal to or higher than the first predetermined threshold.