# US 12,112,798 B2 · Output circuitry for non-volatile memory array in neural network

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- Number: US 12,112,798 B2
- Document ID: US12112798B2
- Status: Granted
- Kind: B2
- Application number: 18/123,918
- Filed: 2023-03-20
- Published: 2023-07-20
- Granted: 2024-10-08
- Earliest claimed: 2016-05-17
- Assignees: Silicon Storage Technology, Inc.
- Applicants: Silicon Storage Technology, Inc.; The Regents of the University of California
- Inventors: Farnood Merrikh Bayat; Xinjie Guo; Dmitri Strukov; Nhan Do; Hieu Van Tran; Vipin Tiwari; Mark Reiten
- Web page: https://patentgrep.com/patent/US12112798B2

## CPC

- G06N 3/065: Analogue means
- G06F 3/061: {Improving I/O performance}
- G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06N 3/04: Architecture, e.g. interconnection topology
- G06N 3/045: Combinations of networks
- G06N 3/0464: Convolutional networks [CNN, ConvNet]
- G06N 3/063: using electronic means
- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/12: Programming voltage switching circuits
- G11C 16/16: for erasing blocks, e.g. arrays, words, groups
- G11C 16/3436: {Arrangements for verifying correct programming or erasure}
- G11C 29/38: Response verification devices
- G11C 2216/04: Nonvolatile memory cell provided with a separate control gate for erasing the cells, i.e. erase gate, independent of the normal read control gate
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Numerous examples are disclosed for an output block coupled to a non-volatile memory array in a neural network and associated methods. In one example, a circuit for converting a current in a neural network into an output voltage comprises a non-volatile memory cell comprises a word line terminal, a bit line terminal, and a source line terminal, wherein the bit line terminal receives the current; and a switch for selectively coupling the word line terminal to the bit line terminal; wherein when the switch is closed, the current flows into the non-volatile memory cell and the output voltage is provided on the bit line terminal.

## Claims

### Claim 1

A circuit for converting a current in a neural network into an output voltage, comprising:
a non-volatile memory cell comprises a word line terminal, a bit line terminal, and a source line terminal, wherein the bit line terminal receives the current; and
a switch for selectively coupling the word line terminal to the bit line terminal;
wherein when the switch is closed, the current flows into the non-volatile memory cell and the output voltage is provided on the bit line terminal.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein the non-volatile memory cell further comprises a control gate terminal.

### Claim 3 (depends on 1)

The circuit of claim 1, wherein the non-volatile memory cell further comprises an erase gate terminal.

### Claim 4 (depends on 1)

The circuit of claim 1, wherein the source line terminal coupled to ground.

### Claim 5 (depends on 1)

The circuit of claim 1, wherein the current is from a neuron in a neural network.

### Claim 6

A circuit for converting a voltage received on an input node into an output current, comprising:
a non-volatile memory cell comprising a word line terminal, a bit line terminal, a source line terminal; and
a switch for selectively coupling the word line terminal to the input node to receive the voltage;
wherein when the switch is closed, the output current is provided on the bit line terminal.

### Claim 7 (depends on 6)

The circuit of claim 6, wherein the non-volatile memory cell further comprises a control gate terminal.

### Claim 8 (depends on 6)

The circuit of claim 6, wherein the non-volatile memory cell further comprises an erase gate terminal.

### Claim 9 (depends on 6)

The circuit of claim 6, wherein the source line terminal is coupled to ground.

### Claim 10 (depends on 6)

The circuit of claim 6, wherein the voltage is received from a neuron in a neural network.

### Claim 11 (depends on 6)

The circuit of claim 6, further comprising clamp circuitry to maintain a fixed voltage on drain of the memory cell.

### Claim 12

A method comprising:
receiving, by a non-volatile memory cell comprising a word line terminal, a bit line terminal, and a source line terminal, a current on the bit line terminal;
coupling, by a switch, the word line terminal to the bit line terminal;
providing, on the bit line terminal, an output voltage.

### Claim 13 (depends on 12)

The method of claim 12, wherein the source line terminal is coupled to ground.

### Claim 14 (depends on 12)

The method of claim 12, wherein the current is received from a neuron in a neural network.

### Claim 15

A method comprising:
receiving, by a non-volatile memory cell comprising a word line terminal, a bit line terminal, and a source line terminal, a voltage on an input node;
coupling, by a switch, the word line terminal to the input node; and
providing, on the bit line terminal, an output current.

### Claim 16 (depends on 15)

The method of claim 15, wherein the source line terminal is coupled to ground.

### Claim 17 (depends on 15)

The method of claim 15, wherein the voltage is received from a neuron in a neural network.