# US 12,112,797 B1 · Cross-layer reconfigurable static random access memory (SRAM) based compute-in-memory macro and method for edge intelligence > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,112,797 B1 - Document ID: US12112797B1 - Status: Granted - Kind: B1 - Application number: 18/602,078 - Filed: 2024-03-12 - Granted: 2024-10-08 - Earliest claimed: 2023-06-13 - Assignees: Shanghai Jiao Tong University - Applicants: Shanghai Jiao Tong University - Inventors: Xinfei Guo; Runxi Wang - Web page: https://patentgrep.com/patent/US12112797B1 ## CPC - G11C 11/419: Read-write [R-W] circuits - G06F 7/505: in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination - G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)} - G11C 11/412: using field-effect transistors only - G11C 11/418: Address circuits - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract The present disclosure provides a cross-layer reconfigurable static random access memory (SRAM) based compute-in-memory (CIM) macro and method for edge intelligence. The cell includes a SRAM cell and a column-shared reconfigurable Boolean computation cell. A reconfiguration computation is performed based on the SRAM cell to obtain a reconfigured structure; the column-shared reconfigurable Boolean computation cell outputs a computation result based on the reconfigured structure; and a peripheral computation circuit supporting pipelined bit-serial addition outputs an in-memory addition result on a basis of a Boolean computation. In order to meet a requirement of edge artificial intelligence (AI) for a low power consumption and a low hardware overhead, and to enable an accelerator to adapt to a fast iterative software algorithm as much as possible. ## Claims ### Claim 1 A cross-layer reconfigurable static random access memory (SRAM) based compute-in-memory (CIM) macro for edge intelligence, comprising a SRAM cell and a column-shared reconfigurable Boolean computation cell, and configured to perform a reconfiguration computation based on the SRAM cell to obtain a reconfigured structure; and output, by the column-shared reconfigurable Boolean computation cell, a computation result based on the reconfigured structure, wherein the SRAM cell has a plurality of transistors and separates a wordline (WL) to obtain a wordline X (WLX) and a wordline Y (WLY); the WLX controls a bitline (BL) to perform reading and writing on the corresponding SRAM cell; the WLY controls a bitline bar (BLB) to perform reading and writing on the corresponding SRAM cell; a plurality of additional transistors connected to a BL and a BLB in each column are column-shared reconfigurable Boolean computation cells; voltage levels of a read wordline PX (RWL_PX) and a read wordline NX (RWL_NX) depend on a mode of a to-be-performed Boolean computation for the BL and an externally input value; voltage levels of a read wordline PY (RWL_PY) and a read wordline NY (RWL_NY) depend on the mode of the to-be-performed Boolean computation for the BLB and the externally input value; and the computation result obtained by the column-shared reconfigurable Boolean computation cell is separately output through a read bitline X (RBL_X) and a read bitline Y (RBL_Y). ### Claim 2 (depends on 1) The cross-layer reconfigurable SRAM based CIM macro for edge intelligence according to claim 1, wherein the column-shared reconfigurable Boolean computation cell supports read, write, AND, OR, and XOR modes; and the column-shared reconfigurable Boolean computation cell is configured by a value of decoded input data and a specific computing mode coming along with RWLs, and computed results are generated in RBLs. ### Claim 3 (depends on 1) The cross-layer reconfigurable SRAM based CIM macro for edge intelligence according to claim 1, wherein on a basis of establishing a SRAM array, CIM supporting pipelined bit-serial addition is established; and in a CIM establishment process, additional computational logic is added to a peripheral circuit of the SRAM array. ### Claim 4 (depends on 3) The cross-layer reconfigurable SRAM based CIM macro for edge intelligence according to claim 3, wherein if a number currently stored in the array is Q, when the number Q and an externally input number IN need to be added up, a carry value of an ith bit and a sum value of an (i+1)th bit are computed simultaneously; and then a value of Qi+1 is read from the BL and a value of Qi′ is read from the BLB, wherein the Qi′ represents an inverse value of Qi, and the Qi represents an ith value in a binary expression sequence of the number Q; a column-shared reconfigurable Boolean computation cell connected to the BL performs an XOR computation on a value of the BL and a corresponding decoded external input INi, and a column-shared reconfigurable Boolean computation cell connected to the BLB uses a value of the BLB and a corresponding decoded external input INi+1 to obtain a Boolean AND result, wherein the INi represents an ith value in a binary expression sequence of the externally input number IN; and a Boolean AND result read from an RBL is input into a pipelined addition peripheral computation circuit, and subsequent computational logic is completed. ### Claim 5 (depends on 3) The cross-layer reconfigurable SRAM based CIM macro for edge intelligence according to claim 3, wherein a multiply accumulate (MAC) operation is established on pipelined bit-parallel addition; an input and a weight of each layer of a neural network are stored in a slice of the SRAM array in different ways; each array has limited storage space and is adjusted based on precision and kernel size requirements during linking; and in a MAC operation process, a logic part of the pipelined bit-parallel addition in the peripheral circuit is reused for a shift-and-add multiplication algorithm. ### Claim 6 (depends on 1) A cross-layer reconfigurable SRAM based CIM method for edge intelligence, applied to the cross-layer reconfigurable SRAM based CIM macro for edge intelligence according to claim 1, and comprising following steps: reconfiguration step: performing a reconfiguration computation based on a SRAM cell to obtain a reconfigured structure; and computation step: outputting, by a column-shared reconfigurable Boolean computation cell, a computation result based on the reconfigured structure, wherein the SRAM cell has a plurality of transistors and separates a wordline (WL) to obtain a wordline X (WLX) and a wordline Y (WLY); the WLX controls a bitline (BL) to perform reading and writing on the corresponding SRAM cell; the WLY controls a bitline bar (BLB) to perform reading and writing on the corresponding SRAM cell; a plurality of additional transistors connected to a BL and a BLB in each column are column-shared reconfigurable Boolean computation cells; voltage levels of a read wordline PX (RWL_PX) and a read wordline NX (RWL_NX) depend on a mode of a to-be-performed Boolean computation for the BL and an externally input value; voltage levels of a read wordline PY (RWL_PY) and a read wordline NY (RWL_NY) depend on the mode of the to-be-performed Boolean computation for the BLB and the externally input value; and the computation result obtained by the column-shared reconfigurable Boolean computation cell is separately output through a read bitline X (RBL_X) and a read bitline Y (RBL_Y). ### Claim 7 (depends on 6) The cross-layer reconfigurable SRAM based CIM method for edge intelligence according to claim 6, wherein the column-shared reconfigurable Boolean computation cell supports read, write, AND, OR, and XOR modes; and the column-shared reconfigurable Boolean computation cell is configured by a value of decoded input data and a specific computing mode coming along with RWLs, and computed results are generated in RBLs. ### Claim 8 (depends on 6) The cross-layer reconfigurable SRAM based CIM method for edge intelligence according to claim 6, wherein on a basis of establishing a SRAM array, CIM supporting pipelined bit-serial addition is established; and in a CIM establishment process, additional computational logic is added to a peripheral circuit of the SRAM array. ### Claim 9 (depends on 8) The cross-layer reconfigurable SRAM based CIM method for edge intelligence according to claim 8, wherein if a number currently stored in the array is Q, when the number Q and an externally input number IN need to be added up, a carry value of an ith bit and a sum value of an (i+1)th bit are computed simultaneously; and then a value of Qi+1 is read from the BL and a value of Qi′ is read from the BLB, wherein the Qi′ represents an inverse value of Qi, and the Qi represents an ith value in a binary expression sequence of the number Q; a column-shared reconfigurable Boolean computation cell connected to the BL performs an XOR computation on a value of the BL and a corresponding decoded external input INi, and a column-shared reconfigurable Boolean computation cell connected to the BLB uses a value of the BLB and a corresponding decoded external input INi+1 to obtain a Boolean AND result, wherein the INi represents an ith value in a binary expression sequence of the externally input number IN; and a Boolean AND result read from an RBL is input into a pipelined addition peripheral computation circuit, and subsequent computational logic is completed. ### Claim 10 (depends on 8) The cross-layer reconfigurable SRAM based CIM method for edge intelligence according to claim 8, wherein a multiply accumulate (MAC) operation is established on pipelined bit-parallel addition; an input and a weight of each layer of a neural network are stored in a slice of the SRAM array in different ways; each array has limited storage space and is adjusted based on precision and kernel size requirements during linking; and in a MAC operation process, a logic part of the pipelined bit-parallel addition in the peripheral circuit is reused for a shift-and-add multiplication algorithm. ### Claim 11 (depends on 6) The cross-layer reconfigurable SRAM based CIM method for edge intelligence according to claim 6, wherein in the computation step, the SRAM cell separates a WL to obtain a WLX and a WLY; the WLX controls a BL to perform reading and writing on the corresponding SRAM cell; the WLY controls a BLB to perform reading and writing on the corresponding SRAM cell; voltage levels of an RWL_PX and an RWL_NX depend on a mode of a to-be-performed Boolean computation for the BL and an externally input value; voltage levels of an RWL_PY and an RWL_NY depend on the mode of the to-be-performed Boolean computation for the BLB and the externally input value; and the computation result obtained by the column-shared reconfigurable Boolean computation cell is separately output through an RBL_X and an RBL_Y. ### Claim 12 (depends on 7) The cross-layer reconfigurable SRAM based CIM method for edge intelligence according to claim 7, wherein in the computation step, the SRAM cell separates a WL to obtain a WLX and a WLY; the WLX controls a BL to perform reading and writing on the corresponding SRAM cell; the WLY controls a BLB to perform reading and writing on the corresponding SRAM cell; voltage levels of an RWL_PX and an RWL_NX depend on a mode of a to-be-performed Boolean computation for the BL and an externally input value; voltage levels of an RWL_PY and an RWL_NY depend on the mode of the to-be-performed Boolean computation for the BLB and the externally input value; and the computation result obtained by the column-shared reconfigurable Boolean computation cell is separately output through an RBL_X and an RBL_Y. ### Claim 13 (depends on 8) The cross-layer reconfigurable SRAM based CIM method for edge intelligence according to claim 8, wherein in the computation step, the SRAM cell separates a WL to obtain a WLX and a WLY; the WLX controls a BL to perform reading and writing on the corresponding SRAM cell; the WLY controls a BLB to perform reading and writing on the corresponding SRAM cell; voltage levels of an RWL_PX and an RWL_NX depend on a mode of a to-be-performed Boolean computation for the BL and an externally input value; voltage levels of an RWL_PY and an RWL_NY depend on the mode of the to-be-performed Boolean computation for the BLB and the externally input value; and the computation result obtained by the column-shared reconfigurable Boolean computation cell is separately output through an RBL_X and an RBL_Y. ### Claim 14 (depends on 9) The cross-layer reconfigurable SRAM based CIM method for edge intelligence according to claim 9, wherein in the computation step, the SRAM cell separates a WL to obtain a WLX and a WLY; the WLX controls a BL to perform reading and writing on the corresponding SRAM cell; the WLY controls a BLB to perform reading and writing on the corresponding SRAM cell; voltage levels of an RWL_PX and an RWL_NX depend on a mode of a to-be-performed Boolean computation for the BL and an externally input value; voltage levels of an RWL_PY and an RWL_NY depend on the mode of the to-be-performed Boolean computation for the BLB and the externally input value; and the computation result obtained by the column-shared reconfigurable Boolean computation cell is separately output through an RBL_X and an RBL_Y. ### Claim 15 (depends on 10) The cross-layer reconfigurable SRAM based CIM method for edge intelligence according to claim 10, wherein in the computation step, the SRAM cell separates a WL to obtain a WLX and a WLY; the WLX controls a BL to perform reading and writing on the corresponding SRAM cell; the WLY controls a BLB to perform reading and writing on the corresponding SRAM cell; voltage levels of an RWL_PX and an RWL_NX depend on a mode of a to-be-performed Boolean computation for the BL and an externally input value; voltage levels of an RWL_PY and an RWL_NY depend on the mode of the to-be-performed Boolean computation for the BLB and the externally input value; and the computation result obtained by the column-shared reconfigurable Boolean computation cell is separately output through an RBL_X and an RBL_Y. ### Claim 16 (depends on 6) The cross-layer reconfigurable SRAM based CIM method for edge intelligence according to claim 6, wherein in the reconfiguration step, on a basis of establishing a SRAM array, CIM supporting pipelined bit-serial addition is established, and additional computational logic is added to a peripheral circuit of the SRAM array. ### Claim 17 (depends on 16) The cross-layer reconfigurable SRAM based CIM method for edge intelligence according to claim 16, wherein in the computation step, if a number currently stored in the array is Q, when the number Q and an externally input number IN need to be added up, a carry value of an ith bit and a sum value of an (i+1)th bit are computed simultaneously; and then a value of Qi+1 is read from the BL and a value of Qi′ is read from the BLB, wherein the Qi′ represents an inverse value of Qi, and the Qi represents an ith value in a binary expression sequence of the number Q; a column-shared reconfigurable Boolean computation cell connected to the BL performs an XOR computation on a value of the BL and a corresponding decoded external input INi, and a column-shared reconfigurable Boolean computation cell connected to the BLB uses a value of the BLB and a corresponding decoded external input INi+1 to obtain a Boolean AND result, wherein the INi represents an ith value in a binary expression sequence of the externally input number IN; and a Boolean AND result read from an RBL is input into a pipelined addition peripheral computation circuit, and subsequent computational logic is completed. ### Claim 18 (depends on 1) A cross-layer reconfigurable SRAM based CIM method for edge intelligence, applied to the cross-layer reconfigurable SRAM based CIM macro for edge intelligence according to claim 1, and comprising following steps: reconfiguration step: performing a reconfiguration computation based on a SRAM cell to obtain a reconfigured structure; and computation step: outputting, by a column-shared reconfigurable Boolean computation cell, a computation result based on the reconfigured structure, wherein in the computation step, the SRAM cell separates a WL to obtain a WLX and a WLY; the WLX controls a BL to perform reading and writing on the corresponding SRAM cell; the WLY controls a BLB to perform reading and writing on the corresponding SRAM cell; voltage levels of an RWL_PX and an RWL_NX depend on a mode of a to-be-performed Boolean computation for the BL and an externally input value; voltage levels of an RWL_PY and an RWL_NY depend on the mode of the to-be-performed Boolean computation for the BLB and the externally input value; and the computation result obtained by the column-shared reconfigurable Boolean computation cell is separately output through an RBL_X and an RBL_Y. ### Claim 19 (depends on 1) A cross-layer reconfigurable SRAM based CIM method for edge intelligence, applied to the cross-layer reconfigurable SRAM based CIM macro for edge intelligence according to claim 1, and comprising following steps: reconfiguration step: performing a reconfiguration computation based on a SRAM cell to obtain a reconfigured structure; and computation step: outputting, by a column-shared reconfigurable Boolean computation cell, a computation result based on the reconfigured structure, wherein in the reconfiguration step, on a basis of establishing a SRAM array, CIM supporting pipelined bit-serial addition is established, and additional computational logic is added to a peripheral circuit of the SRAM array. ### Claim 20 (depends on 19) The cross-layer reconfigurable SRAM based CIM method for edge intelligence according to claim 19, wherein in the computation step, if a number currently stored in the array is Q, when the number Q and an externally input number IN need to be added up, a carry value of an ith bit and a sum value of an (i+1)th bit are computed simultaneously; and then a value of Qi+1 is read from the BL and a value of Qi′ is read from the BLB, wherein the Qi′ represents an inverse value of Qi, and the Qi represents an ith value in a binary expression sequence of the number Q; a column-shared reconfigurable Boolean computation cell connected to the BL performs an XOR computation on a value of the BL and a corresponding decoded external input INi, and a column-shared reconfigurable Boolean computation cell connected to the BLB uses a value of the BLB and a corresponding decoded external input INi+1 to obtain a Boolean AND result, wherein the INi represents an ith value in a binary expression sequence of the externally input number IN; and a Boolean AND result read from an RBL is input into a pipelined addition peripheral computation circuit, and subsequent computational logic is completed.