# US 12,112,796 B2 · Memory circuit and word line driver > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,112,796 B2 - Document ID: US12112796B2 - Status: Granted - Kind: B2 - Application number: 17/674,139 - Filed: 2022-02-17 - Published: 2023-08-17 - Granted: 2024-10-08 - Earliest claimed: 2022-02-17 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company Ltd. - Inventors: Zhi-Hao Chang; Wei-Jer Hsieh - Web page: https://patentgrep.com/patent/US12112796B2 ## CPC - G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines - G11C 11/418: Address circuits - G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge} - G11C 11/413: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction - G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract The present disclosure provides a memory circuit. The memory circuit includes: a plurality of word lines, a word line driver, and a first conductive line. The word line driver is electrically connected to the word lines. The word line driver includes: a plurality of first electronic components and a plurality of second electronic components. The plurality of first electronic components each electrically connected to the corresponding word line. The plurality of second electronic components each having a first terminal and a second terminal. The first terminal is electrically connected to the corresponding word line and the corresponding first electronic component. The first conductive line is electrically connected to the second terminal of the second electronic components. The first conductive line has a length proportional to the number of the word lines. ## Claims ### Claim 1 A memory circuit, comprising: a plurality of word lines; a word line driver electrically connected to the word lines, the word line driver comprising: a plurality of first electronic components; and a plurality of second electronic components each having a first terminal and a second terminal, wherein the first terminal of each of the second electronic components is electrically connected to a respective first electronic component of the plurality of first electronic components, and to a respective word line of the plurality of word lines; a first conductive line electrically connected to the second terminal of each of the second electronic components, wherein the first conductive line has a length proportional to the number of the word lines; and a clamping circuit electrically connected to the first conductive line at a node, wherein the clamping circuit comprises a second conductive line and a first transistor having a drain terminal electrically connected to a first terminal of the second conductive line, a source terminal electrically connected to a voltage supply, and a gate terminal electrically connected to a second terminal of the second conductive line. ### Claim 2 (depends on 1) The memory circuit of claim 1, wherein each of the first electronic components includes an inverter having an input terminal configured to receive a word line select signal and an output terminal configured to provide a word line enable signal in response to the word line select signal, wherein the output terminal of each of the first electronic components is electrically connected to the first terminal of a respective second electronic component of the second electronic components and a respective word line of the plurality of word lines. ### Claim 3 (depends on 2) The memory circuit of claim 2, wherein each of the second electronic components includes a switch, and wherein, when the switch is turned on, an electrical connection between the first conductive line and one word line of the plurality of word lines is established. ### Claim 4 (depends on 1) The memory circuit of claim 1, wherein a curve of a transition of a potential of the one word line of the plurality of word lines has a plurality of humps. ### Claim 5 (depends on 4) The memory circuit of claim 4, wherein a curve of a transition of a potential on the first conductive line has a plurality of humps. ### Claim 6 (depends on 1) The memory circuit of claim 1, wherein the clamping circuit is configured to clamp the first conductive line at a predetermined bias at a standby mode of the memory circuit. ### Claim 7 (depends on 6) The memory circuit of claim 6, wherein the clamping circuit comprises a second transistor having a drain terminal electrically connected to the first conductive line, a source terminal electrically connected to ground, and a gate terminal configured to receive a reset signal. ### Claim 8 (depends on 7) The memory circuit of claim 7, wherein the second terminal of the second conductive line is electrically connected to the drain terminal of the second transistor of the clamping circuit. ### Claim 9 (depends on 8) The memory circuit of claim 8, wherein the gate terminal of the first transistor is electrically connected to the drain terminal of the second transistor of the clamping circuit. ### Claim 10 (depends on 6) The memory circuit of claim 6, wherein the predetermined bias is determined based on the length of the second conductive line. ### Claim 11 A memory circuit, comprising: a plurality of word lines; a word line driver electrically connected to the word lines, the word line driver comprising: a plurality of first electronic components; and a plurality of second electronic components each having a first terminal and a second terminal, wherein the first terminal of each of the second electronic components is electrically connected to a respective first electronic component of the plurality of first electronic components, and to a respective word line of the plurality of word lines: a first conductive line electrically connected to the second terminal of each of the second electronic components, wherein the first conductive line has a length proportional to the number of the word lines; and a clamping circuit electrically connected to the first conductive line at a node, wherein the clamping circuit comprises: a second conductive line having a first terminal and a second terminal opposite to the first terminal; a delay chain having a first terminal configured to receive a first clock signal and a second terminal electrically connected to the first terminal of the second conductive line, and a logic circuit configured to provide a reset signal based on the first clock signal and a second clock signal from the second terminal of the second conductive line. ### Claim 12 (depends on 11) The memory circuit of claim 11, further comprising a plurality of input/output circuits (I/Os), wherein the second conductive line has a second length proportional to the numbers of the I/Os. ### Claim 13 (depends on 11) The memory circuit of claim 11, wherein the clamping circuit is configured to clamp the first conductive line at a predetermined bias at a standby mode of the memory circuit. ### Claim 14 (depends on 11) The memory circuit of claim 11, wherein the clamping circuit comprises a transistor having a drain terminal electrically connected to the first conductive line, a source terminal electrically connected to ground, and a gate terminal configured to receive the reset signal. ### Claim 15 (depends on 11) The memory circuit of claim 11, wherein a curve of a transition of a potential of one word line of the plurality of word lines has a plurality of humps. ### Claim 16 A memory circuit, comprising: a plurality of bit lines; a plurality of word lines; a first conductive line electrically connected to the word lines, wherein the first conductive line has a first length proportional to the numbers of the word lines; a second conductive line having a second length proportional to the number of the bit lines; and a clamping circuit configured to clamp the first conductive line at a predetermined bias at a standby mode of the memory circuit, wherein the clamping circuit is electrically connected to the second conductive line, wherein the predetermined bias is determined based on the length of the second conductive line. ### Claim 17 (depends on 16) The memory circuit of claim 16, further comprising a word line driver electrically connected to the word lines and the first conductive line. ### Claim 18 (depends on 17) The memory circuit of claim 17, wherein the word line driver includes a switch configured to establish an electrical connection between the first conductive line and one of the word lines. ### Claim 19 (depends on 18) The memory circuit of claim 18, further comprising a plurality of memory cells connected to the plurality of bit lines and plurality of word lines, wherein each of the memory cells comprises a static random access memory (SRAM) cell. ### Claim 20 (depends on 18) The memory circuit of claim 18, further comprising a plurality of I/O blocks connected to the bit lines, wherein the number of the I/O blocks is proportional to the number of the bit lines.