# US 12,112,795 B2 · Memory device including predecoder and operating method thereof

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- Number: US 12,112,795 B2
- Document ID: US12112795B2
- Status: Granted
- Kind: B2
- Application number: 17/565,743
- Filed: 2021-12-30
- Published: 2022-12-08
- Granted: 2024-10-08
- Earliest claimed: 2021-06-08
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Kyu Won Choi; Tae Min Choi; Hyeong Cheol Kim; Chan Ho Lee
- Web page: https://patentgrep.com/patent/US12112795B2

## CPC

- G11C 11/418: Address circuits
- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 11/413: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- H03K 19/01742: {by means of a pull-up or down element}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A memory device and operating method of the memory device are provided. The memory device comprises a memory cell storing data based on a first voltage, a row decoder selecting a wordline of the memory cell based on the first voltage, and a wordline predecoder configured to generate a “predec” signal, which is for generating a wordline voltage to be provided to the row decoder. The wordline predecoder is driven by the first voltage and a second voltage, which is different from the first voltage, receives a row address signal, associated with selecting the wordline, and an internal clock signal associated with adjusting operating timings of elements included in the memory device. The wordline predecoder performs a NAND operation on the row address signal and the internal clock signal, and provides the “predec” signal generated based on a result of the NAND operation to the row decoder.

## Claims

### Claim 1

A memory device comprising:
a memory cell configured to store data based on a first voltage;
a row decoder configured to select a wordline of the memory cell based on the first voltage; and
a wordline predecoder configured to generate a “predec” signal associated with generating a wordline voltage to be provided to the row decoder,
wherein the wordline predecoder is
configured to be driven by the first voltage and by a second voltage which is different from the first voltage,
configured to receive a row address signal associated with selecting the wordline, and to receive an internal clock signal associated with adjusting operating timings of elements included in the memory device,
configured to perform a NAND operation on the row address signal and the internal clock signal, and
configured to provide the “predec” signal generated based on a result of the NAND operation to the row decoder, wherein
the performing the NAND operation includes concurrently providing the first voltage to a gate of a first pull-up transistor of a NAND gate, a gate of a second pull-up transistor of the NAND gate, and a gate of a first pull-down transistor of the NAND gate, concurrently with providing the second voltage to a gate of a second pull-down transistor of the NAND gate.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the wordline predecoder includes first and second P-type metal-oxide-semiconductor (PMOS) transistors and first and second N-type metal-oxide-semiconductor (NMOS) transistors, the first and second PMOS transistors and the first and second NMOS transistors configured to be gated by the row address signal or the internal clock signal.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein gates of the first and second PMOS transistors are configured to be at the first voltage.

### Claim 4 (depends on 2)

The memory device of claim 2, wherein a gate of the first NMOS transistor is configured to be at the second voltage.

### Claim 5 (depends on 2)

The memory device of claim 2, wherein a gate of the second NMOS transistor is configured to be at the second voltage.

### Claim 6 (depends on 2)

The memory device of claim 2, further comprising:
a first level shifter,
wherein the first level shifter is configured to level-shift the row address signal from the second voltage to the first voltage and to provide the level-shifted row address signal to the first and second PMOS transistors.

### Claim 7 (depends on 6)

The memory device of claim 6, wherein the first NMOS transistors is configured to be gated by the level-shifted row address signal having the first voltage.

### Claim 8 (depends on 6)

The memory device of claim 6, further comprising:
a second level shifter,
wherein the second level shifter is configured to level-shift the internal clock signal from the second voltage to the first voltage and to provide the level-shifted internal clock signal to the first and second PMOS transistors.

### Claim 9 (depends on 8)

The memory device of claim 8, wherein the second NMOS transistors are configured to be gated by the level-shifted internal clock signal having the first voltage.

### Claim 10 (depends on 1)

The memory device of claim 1, wherein
the row decoder includes a transmission gate and an inverter,
the inverter is connected to an output terminal of the row decoder, and
the memory device is configured to provide the “predec” signal to the transmission gate as an input signal.

### Claim 11 (depends on 1)

The memory device of claim 1, further comprising:
a first level shifter configured to level-shift the row address signal from the second voltage to the first voltage and to provide the level-shifted row address signal to the wordline predecoder; and
a second level shifter configured to level-shift the internal clock signal from the second voltage to the first voltage and to provide the level-shifted internal clock signal to the wordline predecoder.

### Claim 12 (depends on 11)

The memory device of claim 11, wherein
a gate of a first PMOS transistor of the wordline predecoder is configured to be connected to the level-shifted row address signal having the first voltage, and
a gate of a second PMOS transistor of the wordline predecoder is configured to be connected to the level-shifted internal clock signal having the first voltage.

### Claim 13 (depends on 12)

The memory device of claim 12, wherein a gate of an NMOS transistor of the wordline predecoder is configured to be connected to at least one of the row address signal having the second voltage and the internal clock signal having the second voltage.

### Claim 14

A memory device comprising:
a static random-access memory (SRAM) cell connected to a wordline and a bitline;
a wordline driver configured to provide a wordline voltage having a first voltage to the wordline;
a bitline precharge circuit configured to provide a bitline voltage having a second voltage, which is lower than the first voltage, to the bitline; and
a wordline predecoder configured to generate a “predec” signal, which is associated with enabling the wordline voltage,
wherein the wordline predecoder includes
a first pull-up transistor which is configured to pull up the “predec” signal based on a first control signal having the first voltage,
a second pull-up transistor, which is configured to pull up the “predec” signal based on a second control signal having the first voltage,
a first pull-down transistor, which is configured to pull down the “predec” signal based on the second control signal having the second voltage, and
a second pull-down transistor, which is configured to pull down the “predec” signal based on the first control signal having the first voltage, the pulling up based on the first control signal being concurrent with the pulling down based on the second control signal.

### Claim 15 (depends on 14)

The memory device of claim 14, wherein
the first control signal includes an internal clock signal associated with adjusting operating timings of elements included in the memory device, and
the second control signal includes a row address signal associated with selecting the wordline.

### Claim 16 (depends on 14)

The memory device of claim 14, further comprising:
a level shifter,
wherein the level shifter is configured to level-shift the second control signal from the second voltage to the first voltage and to provide the level-shifted second control signal to the wordline predecoder.

### Claim 17 (depends on 14)

The memory device of claim 14, further comprising:
first and second level shifters,
wherein the first and second level shifters are configured to level-shift the second control signal from the second voltage to the first voltage and to provide the level-shifted second control signal to the wordline predecoder.

### Claim 18

An operating method of a memory device, comprising:
allowing an internal clock signal to transition from a first level to a second level;
in response to the internal clock signal transitioning to the second level, allowing a bitline precharge voltage to rise from the first level to the second level at a first time; and
in response to the internal clock signal transitioning to the second level, allowing a wordline voltage to rise from the first level to a third level, which is greater than the second level, at a second time, which is later than the first time.

### Claim 19 (depends on 18)

The operating method of claim 18, further comprising:
allowing the wordline voltage to fall from the third level to the first level at a third time, which is later than the second time; and
allowing the bitline precharge voltage to fall from the second level to the first level at a fourth time, which is later than the third time.