# US 12,112,794 B2 · Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein

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- Number: US 12,112,794 B2
- Document ID: US12112794B2
- Status: Granted
- Kind: B2
- Application number: 18/297,605
- Filed: 2023-04-08
- Published: 2023-08-10
- Granted: 2024-10-08
- Earliest claimed: 2017-10-17
- Assignees: R&D 3 LLC
- Applicants: R&D 3 LLC
- Inventors: Ravindraraj Ramaraju
- Web page: https://patentgrep.com/patent/US12112794B2

## CPC

- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 7/065: {Differential amplifiers of latching type}
- G11C 7/08: Control thereof
- G11C 7/14: Dummy cell management; Sense reference voltage generators
- G11C 7/18: Bit line organisation; Bit line lay-out
- G11C 11/404: with one charge-transfer gate, e.g. MOS transistor, per cell
- G11C 11/4045: {using a plurality of serially connected access transistors, each having a storage capacitor}
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 11/565: {using capacitive charge storage elements}
- G11C 16/30: Power supply circuits
- G11C 8/16: Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
- G11C 11/405: with three charge-transfer gates, e.g. MOS transistors, per cell
- G11C 11/4094: Bit-line management or control circuits
- G11C 2207/2254: Calibration
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

## Claims

### Claim 1

A memory cell, comprising:
multiple data ports, comprising:
a first data port that is a write port for writing data to be stored in the memory cell; and
a second data port that is a read port having a variable impedance that varies in accordance with a data value stored therein, wherein the data value is one of at least three different data values that the memory cell is capable of storing; and
multiple control ports, comprising:
a first control port coupled with the write port; and
a second control port coupled with the read port;
wherein:
the write port is coupled with a write bit line; and
the read port is coupled between a read bit line and a fixed reference.

### Claim 2 (depends on 1)

The memory cell of claim 1, wherein the memory cell is a volatile memory cell.

### Claim 3 (depends on 2)

The memory cell of claim 2, further comprising:
a data node;
a first transistor, comprising:
a first control electrode coupled with a respective control signal of the read port;
a second transistor, comprising:
a second control electrode coupled with the data node; and
a third transistor, comprising:
a third control electrode coupled with a respective control signal of the write port.

### Claim 4 (depends on 3)

The memory cell of claim 3, wherein the memory cell is a 3T DRAM memory cell.

### Claim 5 (depends on 1)

The memory cell of claim 1, wherein:
the read bit line is coupled with multiple read ports that individually correspond to a respective memory cell of a plurality of memory cells; and
at least one read port, of the multiple read ports, provides a variable impedance output configured to perform a function operation when a respective control signal of one or more of the multiple read ports is activated.

### Claim 6 (depends on 5)

The memory cell of claim 5, wherein:
the multiple read ports comprise:
a first read port of a first memory cell; and
a second read port of a second memory cell; and
the function operation is performed when at least a first control signal of the first read port and a second control signal of the second read port are activated.

### Claim 7 (depends on 5)

The memory cell of claim 5, wherein the function operation is an arithmetic function operation.

### Claim 8 (depends on 5)

The memory cell of claim 5, wherein the function operation is a logical function operation.

### Claim 9 (depends on 5)

The memory cell of claim 5, wherein the function operation is a logistic function operation.

### Claim 10 (depends on 1)

The memory cell of claim 1, wherein the fixed reference is a power supply.

### Claim 11

A method, comprising:
storing more than one bit of information in a memory cell, wherein the storing comprises:
writing, though a write port of the memory cell, a data value corresponding to the more than one bit of information, wherein the write port is first data port of multiple data ports of the memory cell, and wherein the write port is coupled with a first control port of multiple control ports of the memory cell; and
determining the more than one bit of information stored in the memory cell, wherein the determining comprises:
reading an output of a read port of the memory cell, wherein the read port has an impedance that varies in accordance with, and is indicative of, the data value stored therein, wherein the data value is one of at least three different data values that the memory cell is capable of storing, wherein the read port is a second data port of the multiple data ports of the memory cell, and wherein the read port is coupled with a second control port of the multiple control ports of the memory cell;
wherein:
the write port is coupled with a write bit line; and
the read port is coupled between a read bit line and a fixed reference.

### Claim 12 (depends on 11)

The method of claim 11, wherein the memory cell is a volatile memory cell.

### Claim 13 (depends on 11)

The method of claim 11, wherein the memory cell is a 3T DRAM memory cell.

### Claim 14 (depends on 11)

The method of claim 11, wherein the output of the read port is configured to perform a function operation.

### Claim 15 (depends on 14)

The method of claim 14, wherein the function operation is an arithmetic operation.

### Claim 16 (depends on 14)

The method of claim 14, wherein the function operation is a logical operation.

### Claim 17 (depends on 14)

The method of claim 14, wherein the function operation is a logistic operation.

### Claim 18 (depends on 14)

The method of claim 14, wherein the function operation is an activation operation.

### Claim 19 (depends on 11)

The method of claim 11, wherein the fixed reference is a power supply.