# US 12,112,793 B2 · Signal routing between memory die and logic die for mode based operations

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- Number: US 12,112,793 B2
- Document ID: US12112793B2
- Status: Granted
- Kind: B2
- Application number: 17/885,374
- Filed: 2022-08-10
- Published: 2023-02-16
- Granted: 2024-10-08
- Earliest claimed: 2021-08-10
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Aliasger T. Zaidy; Glen E. Hush; Sean S. Eilert; Kunal R. Parekh
- Web page: https://patentgrep.com/patent/US12112793B2

## CPC

- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G06F 3/0656: {Data buffering arrangements}
- G06F 13/1673: {using buffers}
- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G11C 7/08: Control thereof
- G11C 7/1039: {using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers}
- G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders}
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G16B 30/00: ICT specially adapted for sequence analysis involving nucleotides or amino acids
- G16B 50/10: Ontologies; Annotations
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- H10W 72/50: Bond wires
- H10W 72/90: Bond pads, in general
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/00: Package configurations
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- G06F 2213/28: DMA
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 7/1012: {Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating}
- H10W 72/01: {Manufacture or treatment}
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/221: {Structures or relative sizes}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/721: {having structure or size changed during the connecting}
- H10W 90/20: Configurations of stacked chips
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/721: {of bump connectors}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/751: {of bond wires}
- H10W 90/752: {between stacked chips}
- H10W 90/792: {between multiple chips}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G16B: BIOINFORMATICS, i.e. INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR GENETIC OR PROTEIN-RELATED DATA PROCESSING IN COMPUTATIONAL MOLECULAR BIOLOGY
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data. The inputs and the outputs to the VV units can be configured based on a mode of the logic die.

## Claims

### Claim 1

A method comprising:
storing, at a buffer of a logic die that is bonded to a memory die via a wafer-on-wafer bonding process, signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and the memory die;
receiving, at the logic die, signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond;
performing, at the logic die, a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data; and
providing results of the plurality of operations to the buffer based on a mode of the logic die and a type of the plurality of operations, wherein the mode of the logic die is used to identify the type of the plurality of operations.

### Claim 2 (depends on 1)

The method of claim 1, further comprising storing the signals indicative of the input data to the buffer and receiving the signals indicative of the kernel data from the LIO lines based on the type of the plurality of operations.

### Claim 3 (depends on 1)

The method of claim 1, further comprising providing the results from the buffer to the memory die via the bond.

### Claim 4 (depends on 1)

The method of claim 1, wherein performing the plurality of operations further comprises performing the plurality of operations at the plurality of VV units, and wherein each of the plurality of VV units receives the signals indicative of the input data from the buffer concurrently.

### Claim 5 (depends on 1)

The method of claim 1, wherein the input data comprises a quantity of bits that is less than or equal to a different quantity of bits that comprises the kernel data.

### Claim 6 (depends on 1)

The method of claim 1, wherein the input data comprises a same quantity of bits as each of a number of portions of the kernel data.

### Claim 7

An apparatus, comprising:
a memory die;
a logic die bonded to the memory die via a wafer-to-wafer bonding process;
wherein the logic die comprises a plurality of vector-vector (VV) units configured to:
receive signals indicative of kernel data from a global data bus (GBUS) of the memory die and through a bond of the logic die and the memory die;
receive signals indicative of input data from local input/output (LIO) lines of the memory die and through the bond;
perform a plurality of operations using the signals indicative of kernel data and the signals indicative of input data; and
provide a plurality of results of the plurality of operations to the LIO lines of the memory die based on a mode of the logic die utilizing a plurality of multiplexors (MUXs).

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the logic die is further configured to provide a result, from the plurality of results, of a VV unit, from the plurality of VV units, via a MUX, from the plurality of MUXs, coupled to the VV unit.

### Claim 9 (depends on 7)

The apparatus of claim 7, wherein each VV unit from the plurality of VV units is coupled to a different MUX from the plurality of MUXs and is configured to provide an output to the different MUX.

### Claim 10 (depends on 7)

The apparatus of claim 7, wherein the logic die is configured to provide the signals indicative of the input data to each of the plurality of VV units based on the mode of the logic die.

### Claim 11 (depends on 7)

The apparatus of claim 7, wherein the logic die is configured to provide the signals indicative of the input data to each of the plurality of VV units based on the mode of the logic die utilizing a different plurality of MUXs.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein each of the different plurality of MUXs is configured to provide a different portion of the input data to each of the plurality of VV units.

### Claim 13 (depends on 11)

The apparatus of claim 11, wherein a quantity of the different plurality of MUXs is less than a quantity of the plurality of MUXs.

### Claim 14 (depends on 11)

The apparatus of claim 11, wherein a quantity of the different plurality of MUXs is less than a quantity of the VV units.

### Claim 15 (depends on 7)

The apparatus of claim 7, wherein a quantity of the VV units is equal to a quantity of the plurality of MUXs.

### Claim 16 (depends on 7)

The apparatus of claim 7, wherein the plurality of VV units is configured to provide the plurality of results of the plurality of operation to the LIO lines via the bond.

### Claim 17 (depends on 7)

The apparatus of claim 7, wherein the logic die is configured to receive the signals indicative of the kernel data and the signals indicative of the input data via a plurality of lines generated via the wafer-on-wafer bonding process that couple the LIO lines and the GBUS to through silicon vias (TSVs).

### Claim 18 (depends on 17)

The apparatus of claim 17, wherein the plurality of VV units is further configured to receive the signals indicative of the kernel data and the signals indicative of the input data from the TSVs.

### Claim 19 (depends on 7)

The apparatus of claim 7, wherein each of the plurality of VV units are further configured to receive the signals indicative of the input data via from a different section of a bank of the memory die via different LIO lines coupled to the different section.

### Claim 20

An apparatus, comprising:
a memory die;
a logic die bonded to the memory die via a wafer-to-wafer bonding process;
wherein the logic die comprises a plurality of vector-vector (VV) units configured to:
receive signals, at a buffer, indicative of first data from a global data bus (GBUS) of the memory die and through bond of the logic die and the memory die;
receive signals, at the plurality of VV units, indicative of second data from local input/output (LIO) lines of the memory die and through the bond;
perform a first plurality of operations using the signals indicative of the first data and the signals indicative of the second data to generate a plurality of outputs;
store the plurality of outputs to the buffer based on the logic die being in a first mode; and
provide the plurality of outputs to the memory die via the LIO lines based on the logic die being in a second mode.

### Claim 21 (depends on 20)

The apparatus of claim 20, wherein the VV units is further configured to:
provide a portion of the plurality of outputs to a portion of the VV units based on the logic die being in a third mode; and
provide the plurality of outputs to the buffer based on the logic die being in the third mode.

### Claim 22 (depends on 20)

The apparatus of claim 20, wherein the VV units are further configured to provide the portion of the plurality of outputs to the portion of the VV units utilizing a first plurality of multiplexors (MUXs) configured using the third mode.

### Claim 23 (depends on 22)

The apparatus of claim 22, wherein the VV units are further configured to provide the plurality of outputs to the buffer utilizing a second plurality of MUXs configured using the third mode.

### Claim 24 (depends on 23)

The apparatus of claim 23, wherein the VV units are configured to store the plurality of outputs to the buffer utilizing the second plurality of MUXs configured utilizing the first mode.

### Claim 25 (depends on 23)

The apparatus of claim 23, wherein the VV units are configured to provide the plurality of outputs to the memory die utilizing the second plurality of MUXs configured utilizing the second mode.

### Claim 26

A method comprising:
storing, at a buffer of a logic die that is bonded to a memory die via a wafer-on-wafer bonding process, signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and the memory die;
receiving, at the logic die, signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond;
performing, at the logic die, a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data;
providing results of the plurality of operations to the buffer based on a mode of the logic die; and
providing the results from the buffer to the memory die via the bond.

### Claim 27

A method comprising:
storing, at a buffer of a logic die that is bonded to a memory die via a wafer-on-wafer bonding process, signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and the memory die;
receiving, at the logic die, signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond;
performing, at the logic die, a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data, wherein each of the plurality of VV units receives the signals indicative of the input data from the buffer concurrently;
providing results of the plurality of operations to the buffer based on a mode of the logic die.

### Claim 28

A method comprising:
storing, at a buffer of a logic die that is bonded to a memory die via a wafer-on-wafer bonding process, signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and the memory die;
receiving, at the logic die, signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond;
performing, at the logic die, a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data, wherein the input data comprises a quantity of bits that is less than or equal to a different quantity of bits that comprises the kernel data;
providing results of the plurality of operations to the buffer based on a mode of the logic die.

### Claim 29

A method comprising:
storing, at a buffer of a logic die that is bonded to a memory die via a wafer-on-wafer bonding process, signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and the memory die;
receiving, at the logic die, signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond;
performing, at the logic die, a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data, wherein the input data comprises a same quantity of bits as each of a number of portions of the kernel data;
providing results of the plurality of operations to the buffer based on a mode of the logic die.