# US 12,112,792 B2 · Memory device for wafer-on-wafer formed memory and logic

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- Number: US 12,112,792 B2
- Document ID: US12112792B2
- Status: Granted
- Kind: B2
- Application number: 17/712,935
- Filed: 2022-04-04
- Published: 2023-02-16
- Granted: 2024-10-08
- Earliest claimed: 2021-08-10
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Glen E. Hush; Sean S. Eilert; Aliasger T. Zaidy; Kunal R. Parekh
- Web page: https://patentgrep.com/patent/US12112792B2

## CPC

- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G06F 3/0656: {Data buffering arrangements}
- G06F 13/1673: {using buffers}
- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G11C 7/08: Control thereof
- G11C 7/1039: {using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers}
- G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders}
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G16B 30/00: ICT specially adapted for sequence analysis involving nucleotides or amino acids
- G16B 50/10: Ontologies; Annotations
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- H10W 72/50: Bond wires
- H10W 72/90: Bond pads, in general
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/00: Package configurations
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- G06F 2213/28: DMA
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 7/1012: {Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating}
- H10W 72/01: {Manufacture or treatment}
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/221: {Structures or relative sizes}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/721: {having structure or size changed during the connecting}
- H10W 90/20: Configurations of stacked chips
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/721: {of bump connectors}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/751: {of bond wires}
- H10W 90/752: {between stacked chips}
- H10W 90/792: {between multiple chips}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G16B: BIOINFORMATICS, i.e. INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR GENETIC OR PROTEIN-RELATED DATA PROCESSING IN COMPUTATIONAL MOLECULAR BIOLOGY
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A memory device includes an array of memory cells configured on a die or chip and coupled to sense lines and access lines of the die or chip and a respective sense amplifier configured on the die or chip coupled to each of the sense lines. Each of a plurality of subsets of the sense lines is coupled to a respective local input/output (I/O) line on the die or chip for communication of data on the die or chip and a respective transceiver associated with the respective local I/O line, the respective transceiver configured to enable communication of the data to one or more device off the die or chip.

## Claims

### Claim 1

An apparatus, comprising:
an array of memory cells configured on a memory die and coupled to sense lines and access lines of the memory die;
a respective sense amplifier configured on the memory die and coupled to each of the sense lines;
a respective local input/output (I/O) line on the memory die and coupled to each of a plurality of subsets of the sense lines for communication of data on the memory die; and
a respective transceiver associated with the respective local I/O line, the respective transceiver configured to enable communication of the data to one or more devices off the memory die, wherein:
the respective transceiver is configured to route the data to the one or more devices off the memory die through the respective local I/O line in response to receipt of a first signal from a controller; and
the respective transceiver is configured to route the data to one or more devices off the memory die through a wafer-on-wafer bond in response to the respective transceiver receiving a second signal from the controller.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the respective transceiver is coupled to the respective local I/O line.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the respective transceiver is coupled to each respective sense amplifier.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the respective transceiver is configured to retrieve data from the sense amplifier.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the respective transceiver is configured to receive a control signal to switch the apparatus between a first mode of operation and a second mode of operation.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the communication of the data to one or more devices off the memory die is disabled in the first mode of operation.

### Claim 7 (depends on 5)

The apparatus of claim 5, wherein the communication of the data to one or more devices off the memory die is enabled in the second mode of operation.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the apparatus is configured for communication of the data on the memory die independent of communication of the data to the one or more devices off the memory die.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein a bandwidth of the communication of the data to one or more devices off the memory die is greater than a bandwidth of the communication of the data on the memory die.

### Claim 10

An apparatus, comprising:
a plurality of tiles coupled to a global input/output (I/O) bus;
each tile including a respective array of memory cells configured on a memory die and coupled to sense lines and access lines of the memory die;
wherein each of a plurality of subsets of the sense lines is coupled to a respective I/O line on the memory die;
wherein local I/O lines are coupled to a global I/O line on the memory die for communication of data on the memory die via the global I/O bus; and
a respective transceiver associated with the respective local I/O line and a wafer-on-wafer bond, wherein:
the respective transceiver is configured to enable communication of the data off the memory die via the respective local I/O line in response to receipt of a first signal from a controller; and
the respective transceiver is configured to enable communication of the data off the memory die via the wafer-on-wafer bond in response to receipt of a second signal from the controller.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the apparatus is configured to simultaneously access a first access line in a row of a first tile and a second access line in a row of a second tile for communication of the data.

### Claim 12 (depends on 10)

The apparatus of claim 10, wherein the apparatus is configured to simultaneously access a first access line in a first row of a first tile and a second access line in a second row of a second tile for communication of the data.

### Claim 13 (depends on 10)

The apparatus of claim 10, wherein the apparatus is configured to access each tile asynchronously.

### Claim 14 (depends on 10)

The apparatus of claim 10, wherein the apparatus is configured to access each tile synchronously.

### Claim 15 (depends on 10)

The apparatus of claim 10, further comprising a respective column decoder coupled to each subset of the sense lines and to the respective local I/O line.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the respective transceiver is coupled between the respective column decoder and the respective local I/O line.

### Claim 17 (depends on 15)

The apparatus of claim 15, wherein the respective transceiver is embedded in the respective column decoder.

### Claim 18 (depends on 15)

The apparatus of claim 15, wherein the respective transceiver is coupled to the local I/O line.

### Claim 19 (depends on 10)

The apparatus of claim 10, further comprising control circuitry coupled to the respective transceiver, wherein the control circuitry is configured to send a control signal to the respective transceiver to enable communication of the data off the memory die.

### Claim 20 (depends on 10)

The apparatus of claim 10, wherein the communication of data on the memory die occurs in a first portion of the apparatus and the communication of data off the memory die occurs in a second portion of the memory device simultaneously.

### Claim 21 (depends on 10)

The apparatus of claim 10, wherein the apparatus is a dynamic random-access memory (DRAM) memory device.

### Claim 22

An apparatus, comprising:
a plurality of memory dies fabricated on a memory wafer;
wherein each of the plurality of memory dies includes:
an array of memory cells;
a plurality of local input/output lines on the plurality of memory dies for communication of data on the plurality of memory dies;
a plurality of transceivers associated with the plurality of local input/output lines on the plurality of memory dies, the plurality of transceivers configured to enable communication of data to one or more memory devices off the plurality of memory dies via the local input/output lines; and
memory-to-logic circuitry coupled to the plurality of transceivers and configured to be coupled to a logic die via a wafer-on-wafer bond, wherein:
each respective transceiver of the plurality of transceivers is configured to enable communication of the data off a respective memory die via a respective local input/output line in response to receipt of a first signal from a controller; and
each respective transceiver of the plurality of transceivers is configured to enable communication of the data off the respective memory die via the wafer-on-wafer bond in response to receipt of a second signal from the controller.

### Claim 23 (depends on 22)

The apparatus of claim 22, wherein the apparatus is a memory wafer.

### Claim 24 (depends on 22)

The apparatus of claim 22, wherein more than one of the plurality of memory dies share memory-to-logic circuitry.

### Claim 25 (depends on 22)

The apparatus of claim 22, wherein at least one memory-to-logic circuitry is configured to be coupled to a plurality of logic dies via the wafer-on-wafer bond.

### Claim 26

A method, comprising:
receiving a signal indicative of data at a sense amplifier configured on a memory die and through a sense line of the memory die;
transferring the signal indicative of data to a multiplexor configured on the memory die coupled to the sense amplifier configured on the memory die;
receiving a control signal to switch a memory device between:
a first mode of operation, wherein the first mode of operation configures the memory device for communication of data on the memory die via local input/output lines; and
a second mode of operation, wherein the second mode of operation configures the memory device for communication of data to one or more devices off the memory die via a wafer-on-wafer bond; and
transferring the signal indicative of data from the multiplexor configured on the memory die to circuitry internal to the memory device or circuitry external to the memory device based on whether the memory device is configured in the first mode of operation or the second mode of operation.

### Claim 27 (depends on 26)

The method of claim 26, further comprising transferring the signal indicative of data from the sense amplifier configured on the memory die to the multiplexor configured on the memory die, a first local input/output line on the memory die, a second local input/output line on the memory die, and a global input/output line on the memory die before the signal indicative of data is used in communication of data on the memory die when the memory device is configured in the first mode of operation.

### Claim 28 (depends on 26)

The method of claim 26, further comprising transferring the signal indicative of data from the sense amplifier configured on the memory die to a transceiver before the signal indicative of data is used in communication of data to one or more devices off the memory die when the memory device is configured in the second mode of operation.