# US 12,112,787 B2 · Apparatuses and methods for access based targeted refresh operations

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- Number: US 12,112,787 B2
- Document ID: US12112787B2
- Status: Granted
- Kind: B2
- Application number: 17/731,645
- Filed: 2022-04-28
- Published: 2023-11-02
- Granted: 2024-10-08
- Earliest claimed: 2022-04-28
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Yuan He; Takamasa Suzuki
- Web page: https://patentgrep.com/patent/US12112787B2

## CPC

- G11C 11/40618: {Refresh operations over multiple banks or interleaving}
- G11C 11/40622: {Partial refresh of memory arrays}
- G11C 11/40603: {Arbitration, priority and concurrent access to memory cells for read/write or refresh operations}
- G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs}
- G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Apparatuses, systems, and methods for access based targeted refresh operations. A memory bank has a first sub-bank and a second sub-bank. A refresh control circuit detects an aggressor in one of the sub-banks. Responsive to an access in the other sub-bank, the refresh control circuit performs a targeted refresh operation based on the sub-bank based on the aggressor address.

## Claims

### Claim 1

A method comprising:
detecting an aggressor address in a first sub-bank of a memory bank;
accessing a word line in a second sub-bank of the memory bank; and
performing a targeted refresh operation on the first sub-bank based on the detected aggressor address responsive to accessing the word line in the second sub-bank.

### Claim 2 (depends on 1)

The method of claim 1, further comprising performing the targeted refresh operation on the first sub-bank responsive to a next access operation in the second sub-bank after detecting the aggressor address in the first sub-bank.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
detecting a second aggressor address in the second sub-bank;
accessing a word line in the first sub-bank; and
performing a targeted refresh operation on the second sub-bank based on the second aggressor address responsive to accessing the word line in the first sub-bank.

### Claim 4 (depends on 1)

The method of claim 1, further comprising periodically performing sequential refresh operations on the first sub-bank.

### Claim 5 (depends on 1)

The method of claim 1, further comprising detecting the aggressor address based on row addresses accessed in the first sub-bank.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
setting an aggressor detected flag responsive to detecting the aggressor address;
comparing a row address associated with the accessed word line to the aggressor address when the flag is set; and
providing a targeted refresh command to the first sub-bank when the row address and the aggressor address are not in the same sub-bank.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
detecting the aggressor address based on a count value stored along an aggressor word line associated with the aggressor address;
accessing the word line or a different word line in the second sub-bank after performing the targeted refresh operation
accessing the word line to reset the count value responsive to accessing the word line or the different word line.

### Claim 8

An apparatus comprising:
a first sub-bank of a memory bank;
a second sub-bank of the memory bank; and
a refresh control circuit configured to identify an aggressor address in the first sub-bank and perform a targeted refresh operation on the first sub-bank based on the aggressor address responsive an access operation on the second sub-bank.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the refresh control circuit comprises an aggressor detector circuit configured to provide a flag and the aggressor address responsive to detecting the aggressor address.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the refresh control circuit includes a comparator configured to compare the aggressor address to an accessed address when flag is set, wherein the refresh control circuit is configured to provide a targeted refresh signal responsive to the comparator determining the aggressor address and the accessed address are not in the same sub-bank.

### Claim 11 (depends on 9)

The apparatus of claim 9, wherein the aggressor detector circuit is configured to identify the aggressor address based on a count value read from memory cells of the aggressor address.

### Claim 12 (depends on 8)

The apparatus of claim 8, wherein the refresh control circuit includes a refresh address generator circuit configured to generate a refresh address based the aggressor address, wherein the targeted refresh operation is performed on a word line associated with the refresh address.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein the refresh address generator circuit is further configured to generate a refresh address responsive to a refresh signal, wherein a sequential refresh operation is performed based on the refresh address and the refresh signal.

### Claim 14 (depends on 8)

The apparatus of claim 8, wherein the refresh control circuit is further configured to identify a second aggressor address in the second sub-bank and perform a targeted refresh operation on the second sub-bank based on the second aggressor address responsive to an access operation on the first sub-bank.