# US 12,112,782 B2 · Compact MRAM architecture with magnetic bottom electrode

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,112,782 B2
- Document ID: US12112782B2
- Status: Granted
- Kind: B2
- Application number: 17/469,350
- Filed: 2021-09-08
- Published: 2023-03-09
- Granted: 2024-10-08
- Earliest claimed: 2021-09-08
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Julien Frougier; Karthik Yogendra; Dimitri Houssameddine; Kangguo Cheng; Ruilong Xie
- Web page: https://patentgrep.com/patent/US12112782B2

## CPC

- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10N 50/01: Manufacture or treatment
- H10N 50/10: Magnetoresistive devices
- H10N 50/80: Constructional details
- H10N 50/85: Materials of the active region
- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

An approach for minimizing stack height and reducing resistance of an MRAM (Magnetoresistive random-access memory) is disclosed. The approach leverages an MRAM device with a T shape magnetic bottom electrode. The T shape magnetic bottom electrode can be made from a lower resistance metal such as cobalt. Furthermore, the method of creating the MRAM can include, depositing a low-k dielectric layer, forming bottom electrode via within the low-k dielectric layer, depositing bottom electrode metal liner on the bottom electrode via, depositing bottom electrode magnetic metal on the bottom electrode metal liner, planarizing the bottom electrode magnetic metal, depositing coupling layer and an MRAM stack on the bottom electrode magnetic metal, patterning and etching anisotropically the MRAM stack and depositing in-situ conformal dielectric layer and forming a top contact via on the MRAM stack.

## Claims

### Claim 1

A compact MRAM (magnetoresistive random-access memory) device with a reduced parasitic resistance capability, the compact MRAM device comprising:
a top electrode coupled on top of a magnetic stack, wherein the magnetic stack further comprises of a free layer, a tunneling barrier, a reference layer, and a coupling layer, in that specific order from top to bottom;
a t-shape magnetic bottom electrode is disposed below and coupled to the coupling layer;
the t-shape magnetic bottom electrode comprising of a horizontal layer being supported by a vertical layer;
a top surface of the horizontal layer of the T-shape magnetic bottom electrode is in direct contact with a bottom surface of the coupling layer and a bottom surface of the vertical layer of T-shape magnetic bottom electrode is in direct contact with a bottom contact, wherein the top surface of the horizontal layer has been under-polished to a low roughness which further reduces stray magnetic field compensation;
a first liner surrounding the top electrode and the magnetic stack;
a first dielectric layer surrounding the first liner;
a metal liner disposed on the t-shape magnetic bottom electrode;
the metal liner envelops the bottom surface of the vertical layer and a bottom surface of the horizontal layer of the T-shape magnetic bottom electrode; and
a second dielectric layer surrounding the metal liner and the bottom contact.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a top metal contact is coupled to the top electrode.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the low roughness is less than 2 nm.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein a bottom interconnect is coupled to the bottom contact.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein T-shape magnetic bottom electrode is a material made of cobalt.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the T-shape magnetic bottom electrode has a thickness level between 20 nm to 50 nm.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor device is a magnetoresistive random access memory (MRAM).

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the T-shape magnetic bottom electrode combined with coupling layer and the reference layer forms an anti-ferromagnetic structure.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the bottom contact further comprises, copper.

### Claim 10

A method for forming a compact MRAM (magnetoresistive random-access memory) device with a reduced parasitic resistance capability, the method comprising:
forming a substrate;
forming a magnetic stack on the T-shape magnetic bottom electrode, wherein the magnetic stack further comprises of a free layer, a tunneling barrier, a reference layer, and a coupling layer;
forming a top electrode on the magnetic stack;
forming a first liner over the top electrode and the magnetic stack;
forming a first dielectric layer over the first liner;
forming a T-shape magnetic bottom electrode on the bottom contact, further comprising:
forming a horizontal layer over a vertical layer, wherein the horizontal layer contains a top surface and a bottom surface and the top surface has been under-polished to a roughness which further reduces stray magnetic field compensation; and
disposing the t-shape magnetic bottom electrode to the coupling layer;
forming an outer metal liner; and
forming a second dielectric layer over the outer metal liner.

### Claim 11 (depends on 10)

The method of claim 10, wherein forming the T-shape bottom electrode further comprises:
forming a via in the first dielectric layer;
depositing a magnetic material on the via; and
planarizing the magnetic material.

### Claim 12 (depends on 10)

The method of claim 10, wherein the T-shape bottom electrode magnetic metal is cobalt.

### Claim 13 (depends on 11)

The method of claim 11, further comprising:
depositing a bottom contact over the substrate.

### Claim 14 (depends on 10)

The method of claim 10, wherein forming the magnetic stack on the T-shape bottom electrode further comprises:
depositing the magnetic stack; and
patterning the magnetic stack.

### Claim 15 (depends on 11)

The method of claim 11, wherein planarizing the magnetic material further comprises:
underpolishing the magnetic material to leave the magnetic material above and within the via.

### Claim 16 (depends on 10)

The method of claim 10, wherein the dielectric layer is made from a low-k dielectric material.

### Claim 17

A computer program product for creating a compact MRAM (magnetoresistive random-access memory) device with a reduced parasitic resistance capability, the computer program product comprising:
one or more computer readable storage media and program instructions stored on the one or more computer readable storage media, the program instructions comprising the steps of:
forming a substrate;
forming a magnetic stack on the T-shape magnetic bottom electrode, wherein the magnetic stack further comprises of a free layer, a tunneling barrier, a reference layer, and a coupling layer;
forming a top electrode on the magnetic stack;
forming a first liner over the top electrode and the magnetic stack;
forming a first dielectric layer over the first liner;
forming a T-shape magnetic bottom electrode on the bottom contact, further comprising:
forming a horizontal layer over a vertical layer, wherein the horizontal layer contains a top surface and a bottom surface and the top surface has been under-polished to a roughness which further reduces stray magnetic field compensation; and
disposing the t-shape magnetic bottom electrode to the coupling layer;
forming an outer metal liner; and
forming a second dielectric layer over the outer metal liner.

### Claim 18 (depends on 17)

The computer program product of claim 17, wherein program instructions to form the T-shape bottom electrode comprises:
forming a via in the first dielectric layer;
depositing a magnetic material on the via; and
planarizing the magnetic material.

### Claim 19 (depends on 17)

The computer program product of claim 17, further comprising:
depositing a bottom contact over the substrate.

### Claim 20 (depends on 17)

The computer program product of claim 17, wherein the T-shape bottom electrode magnetic metal is cobalt.