# US 12,112,718 B2 · Analog video transport integration with display drivers

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- Number: US 12,112,718 B2
- Document ID: US12112718B2
- Status: Granted
- Kind: B2
- Application number: 18/334,692
- Filed: 2023-06-14
- Published: 2023-10-26
- Granted: 2024-10-08
- Earliest claimed: 2021-09-03
- Assignees: HYPHY USA Inc.
- Applicants: Hyfy USA Inc.
- Inventors: Alex Henzen; Todd Rockoff
- Web page: https://patentgrep.com/patent/US12112718B2

## CPC

- G09G 3/3685: {Details of drivers for data electrodes}
- G09G 3/2096: {Details of the interface to the display terminal specific for a flat panel (suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167)}
- G09G 3/3275: Details of drivers for data electrodes
- G09G 3/3614: {Control of polarity reversal in general}
- G09G 3/3674: {Details of drivers for scan electrodes}
- G09G 3/3688: {suitable for active matrices only}
- G06F 3/1407: {General aspects irrespective of display type, e.g. determination of decimal point position, display with fixed or driving decimal point, suppression of non-significant zeros}
- G09G 2310/0275: Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
- G09G 2310/0278: Details of driving circuits arranged to drive both scan and data electrodes
- G09G 2310/0289: Details of voltage level shifters arranged for use in a driving circuit
- G09G 2310/0291: Details of output amplifiers or buffers arranged for use in a driving circuit
- G09G 2310/0294: Details of sampling or holding circuits arranged for use in a driver for data electrodes
- G09G 2330/021: Power management, e.g. power saving
- G09G 2330/06: Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
- G09G 2350/00: Solving problems of bandwidth in display systems
- G09G 2352/00: Parallel handling of streams of display data
- G09G 2360/08: Power processing, i.e. workload management for processors involved in display operations, such as CPUs or GPUs
- G09G 2370/08: Details of image data interface between the display device controller and the data line driver circuit
- G09G 2370/14: Use of low voltage differential signaling [LVDS] for display data communication
- G09G 2370/20: Details of the management of multiple sources of image data
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A video display includes a display panel with gate drivers and source drivers. Each of said the source drivers is arranged to receive a discrete-time continuous-amplitude signal representing a video stream over a transmission medium and to decode the signal using demodulation to produce a plurality of samples for output on outputs of the source drivers. At least one of the source drivers is arranged to extract a gate driver timing control signal from the signal and to output the gate driver control signal to the gate drivers in order to synchronize the gate drivers with outputs of the source drives, whereby the video stream is displayed on the display panel of the display unit.

## Claims

### Claim 1

A video display unit comprising:
a display panel including a plurality of gate drivers and a plurality of source drivers;
a transmitter arranged to receive a video stream in a digital representation, distribute said video stream into input vectors of N digital samples, convert said input vectors of digital samples into ordered sequences of L analog levels, and to transmit said ordered sequences of L analog levels to respective ones of said source drivers; and
each of said source drivers being arranged to receive one of said ordered sequences of L analog levels representing said video stream over a transmission medium from said transmitter within said display unit and to produce a plurality of N analog samples for output on outputs of said each source driver, wherein L>=N>=2, and
whereby said video stream is displayed on said display panel of said display unit.

### Claim 2 (depends on 1)

The video display unit as recited in claim 1 wherein L=N.

### Claim 3 (depends on 2)

The video display unit as recited in claim 2 further comprising:
a decoder for each source driver that decodes said L analog levels with reference to a pre-determined code set of N codes each of length L into an output vector of N analog samples, each of said N codes being associated with one of said samples, wherein said code set is an identity matrix and chip values in said code set are constrained to be “+1” or “0”.

### Claim 4 (depends on 1)

The video display unit as recited in claim 1 further comprising:
a decoder for each source driver that decodes said L analog levels with reference to a pre-determined code set of N mutually-orthogonal codes each of length L into an output vector of N analog samples, each of said N codes being associated with one of said samples, wherein said pre-determined code set is the same as a code set used to encode said series of L analog levels.

### Claim 5 (depends on 1)

The video display unit as recited in claim 1 wherein said each source driver continuously receives ordered sequences of L analog levels and continuously produces N analog samples for output.

### Claim 6 (depends on 1)

A video display unit as recited in claim 1 wherein each of said source drivers does not include a digital-to-analog converter for purposes of converting digital pixel data to analog pixel data.

### Claim 7 (depends on 1)

A video display unit as recited in claim 1 wherein each of said source drivers includes
a buffer arranged to collect output vectors of groups of N analog samples, and to output said collected output vectors of groups of N analog samples in parallel; and
a plurality of amplifiers arranged to receive said collected output vectors and to amplify said analog samples of said collected output vectors and to output each of said analog samples to a column of a display panel.

### Claim 8 (depends on 1)

A video display unit as recited in claim 1 wherein said ordered sequences of L analog levels are discrete-time, continuous-amplitude analog samples.

### Claim 9 (depends on 1)

A video display unit as recited in claim 1 wherein said transmitter is implemented in an integrated circuit separate from a video processor.

### Claim 10 (depends on 1)

A video display unit as recited in claim 1 wherein said transmitter is implemented as a system on module in conjunction with a video processor.

### Claim 11 (depends on 1)

A video display unit as recited in claim 1 wherein said transmitter is integrated within a video processor.

### Claim 12 (depends on 1)

A video display unit as recited in claim 1 wherein said ordered sequences of analog levels are received serially at said each source driver, and wherein said analog samples of said each source driver are output in parallel from said each source driver.

### Claim 13

A source driver comprising:
a receiver within a display unit arranged to receive a plurality of ordered series of L analog input values from a transmitter within said display unit over an electromagnetic pathway, said transmitter being arranged to receive a video stream in a digital representation, convert said video stream into said series of L analog input values, and to transmit said series of L analog input values to said receiver;
a buffer arranged to collect said plurality of ordered series of L analog input values as output vectors of N analog samples each, and to output said output vectors of N analog samples each in parallel, wherein L>=N>=2; and
a plurality of amplifiers arranged to receive said collected output vectors and to amplify said analog samples of said output vectors and to output each of said analog samples to a column of a display panel of said display unit.

### Claim 14 (depends on 13)

The source driver as recited in claim 13 wherein L=N.

### Claim 15 (depends on 14)

The source driver as recited in claim 14 further comprising:
a decoder that decodes said L analog input values with reference to a pre-determined code set of N codes each of length L into said output vector of N analog samples, each of said N codes being associated with one of said samples, wherein said code set is an identity matrix and chip values in said code set are constrained to be “+1” or “0”.

### Claim 16 (depends on 13)

The source driver as recited in claim 13 further comprising:
a decoder that decodes said L analog input values with reference to a pre-determined code set of N mutually-orthogonal codes each of length L into said output vector of N analog samples, each of said N codes being associated with one of said samples, wherein said pre-determined code set is the same as a code set used to encode said ordered series of L analog input values.

### Claim 17 (depends on 13)

The source driver as recited in claim 13 wherein said source driver continuously receives ordered series of L analog levels, said buffer continuously collects output vectors and said amplifiers continuously output analog samples.

### Claim 18 (depends on 13)

A source driver as recited in claim 13 wherein said source driver does not include a digital-to-analog converter (DAC) for purposes of converting digital pixel data to analog pixel data.

### Claim 19 (depends on 13)

A source driver as recited in claim 13 wherein said ordered series of L analog levels are discrete-time, continuous-amplitude analog samples.