# US 12,112,709 B2 · Method of controlling display panel with video data transmitted through eDP/DP interface and related control circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,112,709 B2 - Document ID: US12112709B2 - Status: Granted - Kind: B2 - Application number: 18/080,748 - Filed: 2022-12-14 - Published: 2024-06-20 - Granted: 2024-10-08 - Earliest claimed: 2022-12-14 - Assignees: Novatek Microelectronics Corp. - Applicants: NOVATEK Microelectronics Corp. - Inventors: Yu-Tsung Lu; Chih-Cheng Chuang - Web page: https://patentgrep.com/patent/US12112709B2 ## CPC - G09G 3/3275: Details of drivers for data electrodes - G09G 3/2096: {Details of the interface to the display terminal specific for a flat panel (suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167)} - G09G 2310/0291: Details of output amplifiers or buffers arranged for use in a driving circuit - G09G 2310/0297: Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2370/14: Use of low voltage differential signaling [LVDS] for display data communication - G09G 2370/22: Detection of presence or absence of input display information or of connection or disconnection of a corresponding information source - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A method used for a control circuit for controlling a display panel includes steps of: determining whether there is an input video data received at a predetermined time; outputting an output video data and a clock signal having a first frequency to the display panel when determining that there is an input video data received at the predetermined time; and stopping outputting the output video data but outputting the clock signal having a second frequency to the display panel when determining that there is no input video data received at the predetermined time. Wherein, the second frequency is higher than the first frequency. ## Claims ### Claim 1 A method used for a control circuit, for controlling a display panel, the method comprising: determining whether there is an input video data received at a predetermined time; outputting an output video data and a clock signal having a first frequency to the display panel when determining that there is an input video data received at the predetermined time; and stopping outputting the output video data but outputting the clock signal having a second frequency to the display panel when determining that there is no input video data received at the predetermined time; wherein the second frequency is higher than the first frequency. ### Claim 2 (depends on 1) The method of claim 1, further comprising: outputting an emission pulse signal having a first duty cycle to the display panel in an output frame period for outputting a frame of video data; and outputting the emission pulse signal having a second duty cycle to the display panel in a time period right after the output frame period when determining that there is no input video data received at the predetermined time; wherein the second duty cycle is substantially equal to the first duty cycle. ### Claim 3 (depends on 1) The method of claim 1, further comprising: outputting a gate control signal to the display panel when determining that there is an input video data received at the predetermined time; and stopping outputting the gate control signal to the display panel when determining that there is no input video data received at the predetermined time. ### Claim 4 (depends on 1) The method of claim 1, wherein the step of determining whether there is an input video data received at the predetermined time comprises: counting a line time after reception of a last input video data, to determine whether there is an input video data received at the predetermined time. ### Claim 5 (depends on 4) The method of claim 4, wherein the step of counting the line time after reception of the last input video data comprises: counting a number of blanking start signals received after the reception of the last input video data. ### Claim 6 (depends on 4) The method of claim 4, wherein the step of counting the line time after reception of the last input video data to determine whether there is an input video data received at the predetermined time comprises: determining that there is no input video data received at the predetermined time when no input video data is received after the counted line time exceeds a threshold which is determined according to a line buffer. ### Claim 7 (depends on 1) The method of claim 1, wherein the control circuit is in a normal scan mode when determining that there is an input video data received at the predetermined time, and in a fast scan mode when determining that there is no input video data received at the predetermined time, and the method further comprises: generating a vertical synchronization signal to define an output frame period according to the input video data when the control circuit is in the normal scan mode; and generating the vertical synchronization signal to define a fast scan period in the fast scan mode; wherein a length of the fast scan period is shorter than a length of the output frame period. ### Claim 8 (depends on 1) The method of claim 1, wherein the control circuit is in a fast scan mode, and the method further comprises: entering a normal scan mode and restarting to output the output video data after receiving a blanking end signal which indicates an arrival of the input video data. ### Claim 9 (depends on 1) The method of claim 1, further comprising: receiving the input video data through a display port (DP) interface or an embedded display port (eDP) interface. ### Claim 10 A control circuit for controlling a display panel, comprising: a detection circuit, configured to determine whether there is an input video data received at a predetermined time; a data output driver, coupled to the detection circuit, configured to output an output video data to the display panel when the detection circuit determines that there is an input video data received at the predetermined time, and stop outputting the output video data when the detection circuit determines that there is no input video data received at the predetermined time; and an emission control circuit, coupled to the detection circuit, configured to output a clock signal having a first frequency to the display panel when the detection circuit determines that there is an input video data received at the predetermined time, and output the clock signal having a second frequency to the display panel when the detection circuit determines that there is no input video data received at the predetermined time; wherein the second frequency is higher than the first frequency. ### Claim 11 (depends on 10) The control circuit of claim 10, wherein the emission control circuit is further configured to: output an emission pulse signal having a first duty cycle to the display panel in an output frame period for outputting a frame of video data; and output the emission pulse signal having a second duty cycle to the display panel in a time period right after the output frame period when the detection circuit determines that there is no input video data received at the predetermined time; wherein the second duty cycle is substantially equal to the first duty cycle. ### Claim 12 (depends on 10) The control circuit of claim 10, further comprising a gate control circuit which is configured to: output a gate control signal to the display panel when the detection circuit determines that there is an input video data received at the predetermined time; and stop outputting the gate control signal to the display panel when the detection circuit determines that there is no input video data received at the predetermined time. ### Claim 13 (depends on 10) The control circuit of claim 10, wherein the detection circuit is further configured to count a line time after reception of a last input video data, to determine whether there is an input video data received at the predetermined time. ### Claim 14 (depends on 13) The control circuit of claim 13, wherein the detection circuit is further configured to count a number of blanking start signals received after the reception of the last input video data, to count the line time. ### Claim 15 (depends on 13) The control circuit of claim 13, further comprising a line buffer, wherein the detection circuit is further configured to determine that there is no input video data received at the predetermined time when no input video data is received after the counted line time exceeds a threshold which is determined according to the line buffer. ### Claim 16 (depends on 10) The control circuit of claim 10, wherein the control circuit is in a normal scan mode when the detection circuit determines that there is an input video data received at the predetermined time, and in a fast scan mode when the detection circuit determines that there is no input video data received at the predetermined time, and the control circuit further comprises: a timing controller, configured to: generate a vertical synchronization signal to define an output frame period according to the input video data when the control circuit is in the normal scan mode; and generate the vertical synchronization signal to define a fast scan period in the fast scan mode; wherein a length of the fast scan period is shorter than a length of the output frame period. ### Claim 17 (depends on 10) The control circuit of claim 10, wherein the control circuit is in a fast scan mode, and the control circuit enters a normal scan mode and the data output driver restarts to output the output video data after the control circuit receives a blanking end signal which indicates an arrival of the input video data. ### Claim 18 (depends on 10) The control circuit of claim 10, further configured to receive the input video data through a display port (DP) interface or an embedded display port (eDP) interface. ### Claim 19 A method used for a control circuit, for controlling a display panel, the method comprising: receiving a first frame of video data; outputting the first frame of video data with an emission pulse signal having a first duty cycle to the display panel; determining whether a second frame of video data is received at a predetermined time after the first frame of video data is completely received; and outputting the emission pulse signal having the first duty cycle to the display panel without outputting any video data when determining that the second frame of video data is not received at the predetermined time. ### Claim 20 (depends on 19) The method of claim 19, further comprising: outputting an emission control clock having a first frequency to the display panel for the first frame of video data; and outputting the emission control clock having a second frequency to the display panel when determining that the second frame of video data is not received at the predetermined time; wherein the second frequency is higher than the first frequency. ### Claim 21 (depends on 19) The method of claim 19, further comprising: outputting a gate control signal to the display panel when determining that the second frame of video data is received at the predetermined time; and stopping outputting the gate control signal to the display panel when determining that the second frame of video data is not received at the predetermined time. ### Claim 22 (depends on 19) The method of claim 19, wherein the step of determining whether the second frame of video data is received at the predetermined time comprises: counting a line time after reception of the first frame of video data, to determine whether the second frame of video data is received at the predetermined time. ### Claim 23 (depends on 22) The method of claim 22, wherein the step of counting the line time after reception of the first frame of video data comprises: counting a number of blanking start signals received after the reception of the first frame of video data. ### Claim 24 (depends on 22) The method of claim 22, wherein the step of counting the line time after reception of the first frame of video data to determine whether the second frame of video data is received at the predetermined time comprises: determining that the second frame of video data is not received at the predetermined time when no video data is received after the counted line time exceeds a threshold which is determined according to a line buffer. ### Claim 25 (depends on 19) The method of claim 19, wherein the control circuit is in a normal scan mode when determining that the second frame of video data is received at the predetermined time, and in a fast scan mode when determining that the second frame of video data is not received at the predetermined time, and the method further comprises: generating a vertical synchronization signal to define an output frame period according to the second frame of video data when the control circuit is in the normal scan mode; and generating the vertical synchronization signal to define a fast scan period in the fast scan mode; wherein a length of the fast scan period is shorter than a length of the output frame period. ### Claim 26 (depends on 19) The method of claim 19, wherein the control circuit is in a fast scan mode, and the method further comprises: entering a normal scan mode and restarting to output an output video data after receiving a blanking end signal which indicates an arrival of a third frame of video data. ### Claim 27 (depends on 19) The method of claim 19, further comprising: receiving the first frame of video data through a display port (DP) interface or an embedded display port (eDP) interface. ### Claim 28 A control circuit for controlling a display panel, comprising: a detection circuit, configured to receive a first frame of video data and determine whether a second frame of video data is received at a predetermined time after the first frame of video data is completely received; a data output driver, coupled to the detection circuit, configured to output the first frame of video data to the display panel; and an emission control circuit, coupled to the detection circuit, configured to output an emission pulse signal having a first duty cycle to the display panel; wherein the emission control circuit is further configured to output the emission pulse signal having the first duty cycle and the data output driver is further configured to not output any video data when the detection circuit determines that the second frame of video data is not received at the predetermined time. ### Claim 29 (depends on 28) The control circuit of claim 28, wherein the emission control circuit is further configured to: output an emission control clock having a first frequency to the display panel for the first frame of video data; and output the emission control clock having a second frequency to the display panel when the detection circuit determines that the second frame of video data is not received at the predetermined time; wherein the second frequency is higher than the first frequency. ### Claim 30 (depends on 28) The control circuit of claim 28, further comprising a gate control circuit which is configured to: output a gate control signal to the display panel when the detection circuit determines that the second frame of video data is received at the predetermined time; and stop outputting the gate control signal to the display panel when the detection circuit determines that the second frame of video data is not received at the predetermined time. ### Claim 31 (depends on 28) The control circuit of claim 28, wherein the detection circuit is further configured to count a line time after reception of the first frame of video data, to determine whether the second frame of video data is received at the predetermined time. ### Claim 32 (depends on 31) The control circuit of claim 31, wherein the detection circuit is further configured to count a number of blanking start signals received after the reception of the first frame of video data, to count the line time. ### Claim 33 (depends on 31) The control circuit of claim 31, further comprising a line buffer, wherein the detection circuit is further configured to determine that the second frame of video data is not received at the predetermined time when no video data is received after the counted line time exceeds a threshold which is determined according to the line buffer. ### Claim 34 (depends on 28) The control circuit of claim 28, wherein the control circuit is in a normal scan mode when the detection circuit determines that the second frame of video data is received at the predetermined time, and in a fast scan mode when the detection circuit determines that the second frame of video data is not received at the predetermined time, and the control circuit further comprises: a timing controller, configured to: generate a vertical synchronization signal to define an output frame period according to the second frame of video data when the control circuit is in the normal scan mode; and generate the vertical synchronization signal to define a fast scan period in the fast scan mode; wherein a length of the fast scan period is shorter than a length of the output frame period. ### Claim 35 (depends on 28) The control circuit of claim 28, wherein the control circuit is in a fast scan mode, and the control circuit enters a normal scan mode and the data output driver restarts to output an output video data after the control circuit receives a blanking end signal which indicates an arrival of a third frame of video data. ### Claim 36 (depends on 28) The control circuit of claim 28, further configured to receive the first frame of video data through a display port (DP) interface or an embedded display port (eDP) interface.