# US 12,112,706 B2 · Pixel circuit configured to control light-emitting element

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- Number: US 12,112,706 B2
- Document ID: US12112706B2
- Status: Granted
- Kind: B2
- Application number: 18/308,829
- Filed: 2023-04-28
- Published: 2023-08-24
- Granted: 2024-10-08
- Earliest claimed: 2021-07-21
- Assignees: Wuhan Tianma Micro-Electronics Co., Ltd.
- Applicants: Wuhan Tianma Micro-Electronics Co., Ltd.
- Inventors: Jiro Yanase; Yojiro Matsueda
- Web page: https://patentgrep.com/patent/US12112706B2

## CPC

- G09G 3/3241: the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
- G09G 3/325: the data current flowing through the driving transistor during a setting phase, e.g. by using a switch for connecting the driving transistor to the data driver
- G09G 2230/00: Details of flat display driving waveforms
- G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing
- G09G 2300/0852: being a dynamic memory with more than one capacitor
- G09G 2310/0216: Interleaved control phases for different scan lines in the same sub-field, e.g. initialization, addressing and sustaining in plasma displays that are not simultaneous for all scan lines
- G09G 2310/0251: Precharge or discharge of pixel before applying new pixel voltage
- G09G 2310/061: for resetting or blanking
- G09G 2320/0219: Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
- G09G 2320/0257: Reduction of after-image effects
- G09G 2320/046: Dealing with screen burn-in prevention or compensation of the effects thereof
- G09G 2330/021: Power management, e.g. power saving
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A driving transistor is configured to control driving current for the light-emitting element. A first capacitive element and a second capacitive element are connected in series between a gate and a source of the driving transistor. A first switching transistor is configured to switch connection/disconnection between a data line and an intermediate node located between the first capacitive element and the second capacitive element. A second switching transistor is configured to switch connection/disconnection between the gate and a drain of the driving transistor. A third switching transistor is configured to switch connection/disconnection between the intermediate node and a reference power line. A fourth switching transistor is configured to switch supply/non-supply of driving current from the driving transistor to the light-emitting element. A fifth switching transistor is configured to switch connection/disconnection between an anode of the light-emitting element and a reset power line.

## Claims

### Claim 1

A pixel circuit configured to control light emission of a light-emitting element, the pixel circuit comprising:
a light-emitting element;
a driving transistor configured to control driving current for the light-emitting element;
a first capacitive element and a second capacitive element connected in series between a gate of the driving transistor and a positive power line;
a first switching transistor configured to switch connection/disconnection between the gate of the driving transistor and a data line;
a second switching transistor configured to switch supply/non-supply of electric current from the positive power line to the driving transistor;
a connection line connecting an intermediate node located between the driving transistor and the second switching transistor and an intermediate node located between the first capacitive element and the second capacitive element;
a third switching transistor configured to switch connection/disconnection between the gate of the driving transistor and a reference power line;
a fourth switching transistor configured to switch supply/non-supply of electric current from the driving transistor to the light-emitting element; and
a fifth switching transistor configured to switch connection/disconnection between a reset power line and an intermediate node located between the driving transistor and the fourth switching transistor,
wherein, during an initialization period, the first switching transistor is OFF and the second switching transistor, the third switching transistor, the fourth switching transistor, and the fifth switching transistor are ON,
wherein, during a threshold compensation period following the initialization period, the third switching transistor and the fifth switching transistor are ON and the first switching transistor, the second switching transistor, and the fourth switching transistor are OFF,
wherein, during a data write period following the threshold compensation period, the first switching transistor is ON and the second switching transistor, the third switching transistor, the fourth switching transistor, and the fifth switching transistor are OFF, and
wherein, during an emission period following the data write period, the second switching transistor and the fourth switching transistor are ON and the first switching transistor, the third switching transistor, and the fifth switching transistor are OFF.

### Claim 2 (depends on 1)

The pixel circuit according to claim 1, wherein the first switching transistor, the second switching transistor, the third switching transistor, the fourth switching transistor, and the fifth switching transistor are p-type thin-film transistors.

### Claim 3 (depends on 1)

The pixel circuit according to claim 1, wherein a phase difference θ of a control signal for the first switching transistor with respect to a phase of a signal transmitted by the data line in the initialization period satisfies the following relation:
−π/3≤θ≤0.

### Claim 4 (depends on 1)

The pixel circuit according to claim 1,
wherein the fifth switching transistor is a p-type thin-film transistor, and
wherein the following relation is satisfied:
Vgl≤VEE−6.3V,
where Vgl represents a low potential of a control signal for the fifth switching transistor and VEE represents a cathode potential of the light-emitting element.

### Claim 5 (depends on 1)

The pixel circuit according to claim 1, wherein the first switching transistor, the third switching transistor, and the fifth switching transistor are n-type oxide-semiconductor thin-film transistors, and wherein the driving transistor, the second switching transistor, and the fourth switching transistor are p-type low-temperature polysilicon thin-film transistors.

### Claim 6 (depends on 1)

The pixel circuit according to claim 1 wherein the threshold compensation period is not shorter than 10 μs and not longer than 120 μs.

### Claim 7 (depends on 1)

The pixel circuit according to claim 1, wherein the threshold compensation period is not less than three times and not more than forty times as long as the data write period.