# US 12,112,705 B2 · Pixel, display device, and method of driving display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,112,705 B2 - Document ID: US12112705B2 - Status: Granted - Kind: B2 - Application number: 18/376,160 - Filed: 2023-10-03 - Published: 2024-01-25 - Granted: 2024-10-08 - Earliest claimed: 2021-08-24 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: Hanbit Kim; Taewook Kang; Doo-Na Kim; Sangsub Kim; Yunjung Oh; Dokyeong Lee; Jaehwan Chu - Web page: https://patentgrep.com/patent/US12112705B2 ## CPC - G09G 3/3241: the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror - G09G 3/3291: in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements - G09G 2300/0426: Layout of electrodes and connections - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor - G09G 2300/0852: being a dynamic memory with more than one capacitor - G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes - G09G 2310/0262: The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes - G09G 2310/027: Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters - G09G 2320/0673: for control of gamma adjustment, e.g. selecting another gamma curve - G09G 2330/021: Power management, e.g. power saving - G09G 2330/022: in absence of operation, e.g. no data being entered during a predetermined time - G09G 2340/0435: Change or adaptation of the frame rate of the video stream - G09G 2370/08: Details of image data interface between the display device controller and the data line driver circuit - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A pixel includes an organic light-emitting diode, a driving transistor, a first dual gate transistor, a first capacitor, and a compensation transistor. The organic light-emitting diode includes first and second terminals. The driving transistor generates the driving current and includes a first terminal to which a first power supply voltage is applied, a second terminal connected to the first terminal of the organic light-emitting diode, and a gate terminal. The first dual gate transistor is connected between the gate terminal of the driving transistor and the second terminal of the driving transistor and includes first and second sub-transistors. The first capacitor includes a first electrode to which the first power supply voltage is applied, and a second electrode connected to a first node that connects the first and second sub-transistors to each other. The compensation transistor includes a terminal connected between the second electrode and the first node. ## Claims ### Claim 1 A pixel comprising: an organic light-emitting diode including a first terminal electrically connected to an output node and a second terminal electrically connected to a second power supply voltage line; a driving transistor including a first terminal electrically connected to an input node, a second terminal electrically connected to the output node, and a gate terminal electrically connected to a control node; a first dual gate transistor electrically connected between the control node and the second terminal of the driving transistor, the first dual gate transistor including a first sub-transistor and a second sub-transistor which are connected in series; a first capacitor including a first electrode electrically connected to a first power supply voltage line and a second electrode electrically connected to a first node which connects the first and second sub-transistors to each other; and a compensation transistor including a first terminal to which a compensation voltage is applied, a second terminal electrically connected to the first node, and a gate terminal to which a compensation gate signal is applied. ### Claim 2 (depends on 1) The pixel of claim 1, wherein a voltage level of the compensation voltage is variable according to a gray level, and wherein the compensation voltage is provided to the first node when the compensation transistor is turned on. ### Claim 3 (depends on 1) The pixel of claim 1, further comprising: a second dual gate transistor electrically connected between the control node and an initialization voltage line, the second dual gate transistor including a third sub-transistor and a fourth sub-transistor which are connected in series. ### Claim 4 (depends on 3) The pixel of claim 3, further comprising: a second capacitor including a third electrode electrically connected to the first power supply voltage line and a fourth electrode electrically connected to a second node which connects the third and fourth sub-transistors to each other. ### Claim 5 (depends on 4) The pixel of claim 4, wherein the second terminal of the compensation transistor is electrically connected to the second node, wherein a voltage level of the compensation voltage is variable according to a gray level, and wherein the compensation voltage is provided to the first and second nodes when the compensation transistor is turned on. ### Claim 6 (depends on 5) The pixel of claim 5, wherein, when the pixel is driven at a first frequency, the compensation transistor is turned on in response to the compensation gate signal, such that a deviation between a leakage current at the first node and a leakage current at the second node is reduced by the compensation voltage. ### Claim 7 (depends on 6) The pixel of claim 6, wherein, when the pixel is driven at a second frequency different from the first frequency, the compensation transistor is turned off in response to the compensation gate signal. ### Claim 8 (depends on 7) The pixel of claim 7, wherein the first frequency is greater than about 0 hertz and less than about 60 hertz, and wherein the second frequency is greater than or equal to about 60 hertz and less than or equal to about 240 hertz. ### Claim 9 (depends on 1) The pixel of claim 1, wherein the first dual gate transistor diode-connects the driving transistor in response to a gate signal. ### Claim 10 (depends on 1) The pixel of claim 1, further comprising: a storage capacitor including a first terminal electrically connected to the first power supply voltage line and a second terminal electrically connected to the control node; and a first switching transistor including a first terminal electrically connected to the input node, a second terminal electrically connected to a data line, and a gate terminal to which a gate signal is applied. ### Claim 11 (depends on 1) The pixel of claim 1, further comprising: a second switching transistor including a first terminal electrically connected to the first power supply voltage line, a second terminal electrically connected to the input node, and a gate terminal to which an emission signal is applied; and a third switching transistor including a first terminal electrically connected to the second terminal of the driving transistor, a second terminal electrically connected to the output node, and a gate terminal to which the emission signal is applied. ### Claim 12 (depends on 1) The pixel of claim 1, further comprising: a fourth switching transistor including a first terminal electrically connected to an initialization voltage line, a second terminal electrically connected to the output node, and a gate electrode to which an anode initialization signal is applied. ### Claim 13 A display device comprising: a display panel including pixels, each of the pixels including: an organic light-emitting diode including a first terminal electrically connected to an output node and a second terminal electrically connected to a second power supply voltage line; a driving transistor including a first terminal electrically connected to an input node, a second terminal electrically connected to the output node, and a gate terminal electrically connected to a control node; a first dual gate transistor electrically connected between the control node and the second terminal of the driving transistor, the first dual gate transistor including a first sub-transistor and a second sub-transistor which are connected in series; a first capacitor including a first electrode electrically connected to a first power supply voltage line and a second electrode electrically connected to a first node which connects the first and second sub-transistors to each other; and a compensation transistor including a first terminal to which a compensation voltage is applied, a second terminal electrically connected to the first node, and a gate terminal to which a compensation gate signal is applied; a data driver which generates a data voltage corresponding to input image data and supplies the data voltage to the pixels; and a compensation driver which receives gray level data from the data driver and generates the compensation voltage. ### Claim 14 (depends on 13) The display device of claim 13, wherein a voltage level of the compensation voltage is variable according to a gray level, and wherein the compensation voltage is provided to the first node when the compensation transistor is turned on. ### Claim 15 (depends on 13) The display device of claim 13, wherein each of the pixels further includes: a second dual gate transistor electrically connected between the control node and an initialization voltage line, the second dual gate transistor including a third sub-transistor and a fourth sub-transistor which are connected in series; and a second capacitor including a third electrode electrically connected to the first power supply voltage line and a fourth electrode electrically connected to a second node which connects the third and fourth sub-transistors to each other. ### Claim 16 (depends on 15) The display device of claim 15, wherein the second terminal of the compensation transistor is electrically connected to the second node, wherein a voltage level of the compensation voltage is variable according to a gray level, and wherein the compensation voltage is provided to the first and second nodes when the compensation transistor is turned on. ### Claim 17 (depends on 16) The display device of claim 16, wherein the compensation driver provides the compensation gate signal and the compensation voltage to the compensation transistor when the pixel is driven at a first frequency. ### Claim 18 (depends on 17) The display device of claim 17, wherein the compensation driver includes: a memory which stores compensation voltage data for reducing a deviation between a leakage current at the first node and a leakage current at the second node according to a gray level; a calculator which receives the gray level data and determines the compensation voltage corresponding to the gray level among the compensation voltage data; and a signal generator which generates the compensation voltage and the compensation gate signal. ### Claim 19 (depends on 13) The display device of claim 13, wherein each of the pixels further includes: a storage capacitor including a first terminal electrically connected to the first power supply voltage line and a second terminal electrically connected to the control node; a first switching transistor including a first terminal electrically connected to the input node, a second terminal electrically connected to a data line, and a gate terminal to which a gate signal is applied; a second switching transistor including a first terminal electrically connected to the first power supply voltage line, a second terminal electrically connected to the input node, and a gate terminal to which an emission signal is applied; a third switching transistor including a first terminal electrically connected to the second terminal of the driving transistor, a second terminal electrically connected to the output node, and a gate terminal to which the emission signal is applied; and a fourth switching transistor including a first terminal electrically connected to an initialization voltage line, a second terminal electrically connected to the output node, and a gate electrode to which an anode initialization signal is applied. ### Claim 20 (depends on 13) The display device of claim 13, further comprising: a gate driver which generates a gate signal to supply the gate signal to the pixels; an emission driver which generates an emission signal to supply the emission signal to the pixels; a power supply unit which generates a first power supply voltage, an initialization voltage, and a second power supply voltage to provide the first power supply voltage, the initialization voltage, and the second power supply voltage to the pixels; and a controller which generates the input image data to provide the input image data to the data driver.