# US 12,112,704 B2 · Pixel circuit and display device including the same

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- Number: US 12,112,704 B2
- Document ID: US12112704B2
- Status: Granted
- Kind: B2
- Application number: 18/501,031
- Filed: 2023-11-03
- Published: 2024-07-18
- Granted: 2024-10-08
- Earliest claimed: 2023-01-12
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Yeonkyung Kim; Kwihyun Kim; Dongwoo Kim
- Web page: https://patentgrep.com/patent/US12112704B2

## CPC

- G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element
- G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing
- G09G 2300/0852: being a dynamic memory with more than one capacitor
- G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2320/045: Compensation of drifts in the characteristics of light emitting or modulating elements
- G09G 2330/021: Power management, e.g. power saving
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A pixel circuit is disclosed that includes first through sixth transistors, first and second capacitors, and a light emitting element. A gate electrode of the second transistor receives a first gate signal. A gate electrode of the third transistor receive a second gate signal. Gate electrodes of each of the fourth and fifth transistors receive a third gate signal. A gate electrode of the sixth transistor receives an emission signal. First electrodes of the first transistor and the first capacitor each receive a first power supply voltage. A cathode electrode of the light emitting element receives a second power supply voltage. A first electrode of the fourth transistor receives an initialization voltage.

## Claims

### Claim 1

A pixel circuit, comprising:
a first transistor including a gate electrode connected to a first node, a first electrode which receives a first power supply voltage, and a second electrode connected to a second node;
a second transistor including a gate electrode which receives a first gate signal, a first electrode connected to a data line, and a second electrode connected to a fourth node;
a third transistor including a gate electrode which receives a second gate signal, a first electrode connected to the second node, and a second electrode connected to the first node;
a fourth transistor including a gate electrode which receives a third gate signal, a first electrode which receives an initialization voltage, and a second electrode connected to the first node;
a fifth transistor including a gate electrode which receives the third gate signal, a first electrode connected to the first node, and a second electrode connected to a third node;
a sixth transistor including a gate electrode which receives an emission signal, a first electrode connected to the second node, and a second electrode connected to the third node;
a first capacitor including a first electrode which receives the first power supply voltage and a second electrode connected to the first node;
a second capacitor including a first electrode connected to the fourth node and a second electrode connected to the first node; and
a light emitting element including an anode electrode connected to the third node and a cathode electrode which receives a second power supply voltage.

### Claim 2 (depends on 1)

The pixel circuit of claim 1, wherein a frame period in which the pixel circuit is driven includes an initialization period, a threshold voltage compensation period, a data writing period, and a light emission period,
wherein, during the initialization period, an initialization operation for initializing the fourth node, the first node, and the third node is performed,
wherein, during the threshold voltage compensation period, a threshold voltage compensating operation for compensating for a threshold voltage of the first transistor is performed,
wherein, during the data writing period, a data writing operation for writing a data voltage to the first node is performed, and
wherein, during the light emission period, a light emitting operation for controlling the light emitting element to emit light is performed.

### Claim 3 (depends on 2)

The pixel circuit of claim 2, wherein, during the initialization period, the fourth transistor and the fifth transistor are turned on in response to the third gate signal such that the initialization voltage is applied to the first node and the third node.

### Claim 4 (depends on 2)

The pixel circuit of claim 2, wherein, during the initialization period, a reference voltage is applied to the data line and the second transistor is turned on in response to the first gate signal such that the reference voltage is applied to the fourth node.

### Claim 5 (depends on 2)

The pixel circuit of claim 2, wherein, during the threshold voltage compensation period, the third transistor is turned on in response to the second gate signal such that the third transistor diode-connects the first transistor.

### Claim 6 (depends on 5)

The pixel circuit of claim 5, wherein, when the first transistor is diode-connected, a voltage of the first node has a value obtained by adding a threshold voltage of the first transistor to the first power supply voltage.

### Claim 7 (depends on 2)

The pixel circuit of claim 2, wherein, during the data writing period, the data voltage is applied to the data line and the second transistor is turned on in response to the first gate signal such that the data voltage is applied to the fourth node.

### Claim 8 (depends on 7)

The pixel circuit of claim 7, wherein, during the data writing period, the second transistor is turned on in response to the first gate signal and a voltage of the fourth node is changed from a reference voltage to the data voltage, such that a voltage of the first node is boosted by a boosting voltage by the first capacitor and the second capacitor.

### Claim 9 (depends on 8)

The pixel circuit of claim 8, wherein the boosting voltage is determined by using an [Equation] below:
ΔVN1={C_C2/(C_C1+C_C2)}×ΔVN4,
where ΔVN1 denotes the boosting voltage, C_C1 denotes a capacitance of the first capacitor, C_C2 denotes a capacitance of the second capacitor, and ΔVN4 denotes a voltage variation of the fourth node.

### Claim 10 (depends on 2)

The pixel circuit of claim 2, wherein, during the light emission period, the sixth transistor is turned on in response to the emission signal such that the light emitting element emits light based on a driving current of the first transistor.

### Claim 11

A display device, comprising:
a display panel including a pixel circuit; and
a display panel driver configured to drive the display panel,
wherein the pixel circuit include:
a first transistor including a gate electrode connected to a first node, a first electrode which receives a first power supply voltage, and a second electrode connected to a second node;
a second transistor including a gate electrode which receives a first gate signal, a first electrode connected to a data line, and a second electrode connected to a fourth node;
a third transistor including a gate electrode which receives a second gate signal, a first electrode connected to the second node, and a second electrode connected to the first node;
a fourth transistor including a gate electrode which receives a third gate signal, a first electrode which receives an initialization voltage, and a second electrode connected to the first node;
a fifth transistor including a gate electrode receiving the third gate signal, a first electrode connected to the first node, and a second electrode connected to a third node;
a sixth transistor including a gate electrode which receives an emission signal, a first electrode connected to the second node, and a second electrode connected to the third node;
a first capacitor including a first electrode which receives the first power supply voltage and a second electrode connected to the first node;
a second capacitor including a first electrode connected to the fourth node and a second electrode connected to the first node; and
a light emitting element including an anode electrode connected to the third node and a cathode electrode which receives a second power supply voltage.

### Claim 12 (depends on 11)

The display device of claim 11, wherein a frame period in which the pixel circuit is driven includes an initialization period, a threshold voltage compensation period, a data writing period, and an light emission period,
wherein, during the initialization period, an initialization operation for initializing the fourth node, the first node, and the third node is performed,
wherein, during the threshold voltage compensation period, a threshold voltage compensating operation for compensating a threshold voltage of the first transistor is performed,
wherein, during the data writing period, a data writing operation for writing a data voltage to the first node is performed, and
wherein, during the light emission period, a light emitting operation for controlling the light emitting element to emit light is performed.

### Claim 13 (depends on 12)

The display device of claim 12, wherein, during the initialization period, the fourth transistor and the fifth transistor are turned on in response to the third gate signal such that the initialization voltage is applied to the first node and the third node.

### Claim 14 (depends on 12)

The display device of claim 12, wherein, during the initialization period, a reference voltage is applied to the data line and the second transistor is turned on in response to the first gate signal such that the reference voltage is applied to the fourth node.

### Claim 15 (depends on 12)

The display device of claim 12, wherein, during the threshold voltage compensation period, the third transistor is turned on in response to the second gate signal such that the third transistor diode-connects the first transistor.

### Claim 16 (depends on 15)

The display device of claim 15, wherein, when the first transistor is diode-connected, a voltage of the first node has a value obtained by adding a threshold voltage of the first transistor to the first power supply voltage.

### Claim 17 (depends on 12)

The display device of claim 12, wherein, during the data writing period, the data voltage is applied to the data line and the second transistor is turned on in response to the first gate signal such that the data voltage is applied to the fourth node.

### Claim 18 (depends on 17)

The display device of claim 17, wherein, during the data writing period, the second transistor is turned on in response to the first gate signal and a voltage of the fourth node is changed from a reference voltage to the data voltage, such that a voltage of the first node is boosted by a boosting voltage by the first capacitor and the second capacitor.

### Claim 19 (depends on 18)

The display device of claim 18, wherein the boosting voltage is determined by using an [Equation] below:
ΔVN1={C_C2/(C_C1+C_C2)}×ΔVN4,
where ΔVN1 denotes the boosting voltage, C_C1 denotes a capacitance of the first capacitor, C_C2 denotes a capacitance of the second capacitor, and ΔVN4 denotes a voltage variation of the fourth node.

### Claim 20 (depends on 12)

The display device of claim 12, wherein, during the light emission period, the sixth transistor is turned on in response to the emission signal such that the light emitting element emits light based on a driving current of the first transistor.
