# US 12,112,701 B2 · Display device

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- Number: US 12,112,701 B2
- Document ID: US12112701B2
- Status: Granted
- Kind: B2
- Application number: 18/321,900
- Filed: 2023-05-23
- Published: 2024-03-21
- Granted: 2024-10-08
- Earliest claimed: 2022-09-16
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Danwon Lim; Hyunjoon Kim; Bon-Yong Koo
- Web page: https://patentgrep.com/patent/US12112701B2

## CPC

- G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10D 86/60: wherein the TFTs are in active matrices
- H10K 59/131: Interconnections, e.g. wiring lines or terminals
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing
- G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
- G09G 2310/0251: Precharge or discharge of pixel before applying new pixel voltage
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2320/0223: Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
- H10K 59/1213: {the pixel elements being TFTs}
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

A display device includes a display panel including a first pixel, a second pixel, and a connection line connecting the first pixel and the second pixel. Each of the first pixel and the second pixel includes a light emitting element, a first transistor including a first electrode, a second electrode electrically connected to the light emitting element, and a gate electrode, a second transistor connected between a first driving voltage line and a connection node and including a gate electrode connected to an emission line, a third transistor connected between a second driving voltage line and the connection node and including a gate electrode connected to the emission line, and a capacitor connected between the gate electrode of the first transistor and the connection node. The connection node of the first pixel is electrically connected to the connection node of the second pixel through the connection line.

## Claims

### Claim 1

A display device comprising:
a display panel including:
a first pixel;
a second pixel; and
a connection line electrically connecting the first pixel and the second pixel, wherein
each of the first pixel and the second pixel includes:
a light emitting element;
a first transistor including a first electrode, a second electrode electrically connected to the light emitting element, and a gate electrode;
a second transistor electrically connected between a first driving voltage line and a connection node and including a gate electrode electrically connected to an emission line;
a third transistor electrically connected between a second driving voltage line and the connection node and including a gate electrode electrically connected to the emission line;
a fifth transistor electrically connected between the second transistor and the first electrode of the first transistor and including a gate electrode electrically connected to the emission line; and
a capacitor electrically connected between the gate electrode of the first transistor and the connection node, and
the connection node of the first pixel is electrically connected to the connection node of the second pixel through the connection line.

### Claim 2 (depends on 1)

The display device of claim 1, wherein
a compensation voltage from the second driving voltage line is provided to the connection node of each of the first pixel and the second pixel by the third transistor upon an emission signal provided to the emission line being at a first level, and
a first driving voltage from the first driving voltage line is provided to the connection node of each of the first pixel and the second pixel by the second transistor upon the emission signal provided to the emission line being at a second and different level.

### Claim 3 (depends on 1)

The display device of claim 1, wherein
each of the first transistor and the second transistor is a P-type transistor, and
the third transistor is an N-type transistor.

### Claim 4 (depends on 1)

The display device of claim 1, wherein each of the first pixel and the second pixel further comprises:
a fourth transistor electrically connected between the gate electrode of the first transistor and a third driving voltage line;
a sixth transistor electrically connected between the second electrode of the first transistor and an anode of the light emitting element and including a gate electrode electrically connected to the emission line;
a seventh transistor electrically connected between the anode of the light emitting element and a fourth driving voltage line and including a gate electrode electrically connected to the emission line;
an eighth transistor electrically connected between the second electrode of the first transistor and the gate electrode of the first transistor;
a ninth transistor electrically connected between a data line and the first electrode of the first transistor; and
a tenth transistor electrically connected between the first electrode of the first transistor and a fifth driving voltage line.

### Claim 5 (depends on 4)

The display device of claim 4, wherein
each of the fifth transistor, the sixth transistor, the ninth transistor, and the tenth transistor is a P-type transistor, and
each of the fourth transistor, the seventh transistor, and the eighth transistor is an N-type transistor.

### Claim 6 (depends on 1)

The display device of claim 1, wherein
during a non-emission period, the light emitting element does not emit light, and a compensation voltage from the second driving voltage line is provided to the connection node of each of the first pixel and the second pixel by the third transistor, and
during an emission period, the light emitting element emits light, and a first driving voltage from the first driving voltage line is provided to the connection node of each of the first pixel and the second pixel by the second transistor.

### Claim 7 (depends on 1)

The display device of claim 1, wherein
the display panel further includes a third pixel, and
the connection line electrically connects the first pixel, the second pixel, and the third pixel.

### Claim 8 (depends on 7)

The display device of claim 7, wherein the second driving voltage line further comprises:
a horizontal driving voltage line extending in a first direction; and
a vertical driving voltage line electrically connected to the horizontal driving voltage line and extending in a second direction intersecting the first direction, wherein the vertical driving voltage line is disposed adjacent to the third pixel.

### Claim 9

A display device comprising:
a display panel including:
a first pixel;
a second pixel; and
a connection line electrically connecting the first pixel and the second pixel,
wherein
each of the first pixel and the second pixel includes:
a light emitting element;
a first transistor including a first electrode, a second electrode, and a gate electrode;
a second transistor including a first electrode electrically connected to the connection line, a second electrode electrically connected to a first driving voltage line, and a gate electrode electrically connected to an emission line;
a third transistor including a first electrode electrically connected to the connection line, a second electrode electrically connected to a second driving voltage line, and a gate electrode electrically connected to the emission line; and
a capacitor electrically connected between the gate electrode of the first transistor and the connection line,
the connection line is disposed to overlap in a plan view the gate electrode of the first transistor of the first pixel and the gate electrode of the first transistor of the second pixel such that overlapping parts of the connection line and gate electrode of the first transistor of each of the first and second pixels form the capacitor of each of the first and second pixels, respectively.

### Claim 10 (depends on 9)

The display device of claim 9, wherein each of the first pixel and the second pixel further comprises a connection node, wherein the connection node of each of the first pixel and the second pixel is electrically connected to:
the first electrode of the second transistor through a first contact hole,
the first electrode of the third transistor through a second contact hole, and
the connection line through a third contact hole.

### Claim 11 (depends on 10)

The display device of claim 10, wherein
the connection line extends in a first direction,
a branch part extends from the connection line in a second direction intersecting the first direction, and
the branch part is electrically connected to the connection node through the third contact hole.

### Claim 12 (depends on 10)

The display device of claim 10, wherein
the display panel further comprises:
a base layer;
a first insulating layer disposed on the base layer; and
a second insulating layer disposed on the first insulating layer,
the first transistor, the second transistor, and the connection line are disposed between the base layer and the first insulating layer,
the third transistor is disposed between the first insulating layer and the second insulating layer, and
the connection node is disposed on the second insulating layer.

### Claim 13 (depends on 12)

The display device of claim 12, wherein the connection line is connected to:
the first electrode of the second transistor through the first contact hole passing through both the first insulating layer and the second insulating layer,
the second electrode of the third transistor through the second contact hole passing through the second insulating layer, and
the connection node through the third contact hole passing through both the first insulating layer and the second insulating layer.

### Claim 14 (depends on 10)

The display device of claim 10, wherein
a compensation voltage from the second driving voltage line is provided to the connection node of each of the first pixel and the second pixel by the third transistor upon an emission signal provided to the emission line being at a first level, and
a first driving voltage from the first driving voltage line is provided to the connection node of each of the first pixel and the second pixel by the second transistor upon the emission signal provided to the emission line being at a second and different level.

### Claim 15 (depends on 9)

The display device of claim 9, wherein the connection line is spaced apart from the second driving voltage line in a second direction.

### Claim 16 (depends on 9)

The display device of claim 9, wherein the connection line is disposed to overlap in a plan view the first driving voltage line.

### Claim 17 (depends on 9)

The display device of claim 9, wherein
each of the first transistor and the second transistor is a P-type transistor, and
the third transistor is an N-type transistor.

### Claim 18 (depends on 9)

The display device of claim 9, wherein each of the first pixel and the second pixel further comprises:
a fourth transistor electrically connected between the gate electrode of the first transistor and a third driving voltage line;
a fifth transistor electrically connected between the second transistor and the first electrode of the first transistor and including a gate electrode electrically connected to the emission line;
a sixth transistor electrically connected between the second electrode of the first transistor and an anode of the light emitting element and including a gate electrode electrically connected to the emission line;
a seventh transistor electrically connected between the anode of the light emitting element and a fourth driving voltage line and including a gate electrode electrically connected to the emission line;
an eighth transistor electrically connected between the second electrode of the first transistor and the gate electrode of the first transistor;
a ninth transistor electrically connected between a data line and the first electrode of the first transistor; and
a tenth transistor electrically connected between the first electrode of the first transistor and a fifth driving voltage line.

### Claim 19 (depends on 18)

The display device of claim 18, wherein
each of the fifth transistor, the sixth transistor, the ninth transistor, and the tenth transistor is a P-type transistor, and
each of the fourth transistor, the seventh transistor, and the eighth transistor is an N-type transistor.

### Claim 20 (depends on 9)

The display device of claim 9, wherein
the display panel further comprises a third pixel,
the connection line electrically connects to each of the first pixel, the second pixel, and the third pixel,
the second driving voltage line further includes:
a horizontal driving voltage line extending in a first direction; and
a vertical driving voltage line electrically connected to the horizontal driving voltage line and extending in a second direction intersecting the first direction, and the vertical driving voltage line is disposed adjacent to the third pixel.