# US 12,112,699 B2 · Pixel driving circuit having reduced number of contacts

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- Number: US 12,112,699 B2
- Document ID: US12112699B2
- Status: Granted
- Kind: B2
- Application number: 18/032,461
- Filed: 2021-12-02
- Published: 2023-12-07
- Granted: 2024-10-08
- Earliest claimed: 2020-12-04
- Assignees: Sapien Semiconductors Inc.
- Applicants: Sapien Semiconductors Inc.
- Inventors: Jae Hoon Lee; Ji Han Kim
- Web page: https://patentgrep.com/patent/US12112699B2

## CPC

- G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED]
- G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element
- G09G 3/2022: {using sub-frames}
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2310/0243: Details of the generation of driving signals
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

The present specification discloses a pixel driving circuit having a reduced number of external contacts. A conventional digital driving pixel requires two contacts (Vcc, GND) related to power, a contact (row signal, column signal) for inputting two signals for digital driving, a contact (mode selection) for inputting a set value required for driving the pixel, and a contact (reset) for maintaining video data for one frame to implement a cycle function during PWM driving and for inputting a reset signal to clear previous video data before inputting new video data. However, the higher the number of contacts, the lower the efficiency of pick & place in the manufacturing process. Thus, in the present specification, a pixel driving circuit is proposed, which can be digitally driven even when the number of contacts is reduced through combination of a row signal and a column signal.

## Claims

### Claim 1

A pixel driving circuit comprising:
a pixel internal memory comprising a plurality of memory cells configured to store a setting value related to stored data comprising pixel driving data and video data;
a signal detection circuit comprising a row signal input terminal and a column signal input terminal;
a first low-pass filter configured to output a first signal, which has a first frequency lower than a preset first cutoff frequency, from a signal output from the signal detection circuit; and
a second low-pass filter configured to output a second signal, which has a second frequency lower than a preset second cutoff frequency, from the signal output from the signal detection circuit to the pixel internal memory,
wherein the pixel internal memory comprises:
a single flag memory cell configured to store a mode value;
a setting data shift register having a plurality of setting memory cells configured to store the setting value related to pixel driving; and
K video data shift registers corresponding to a number of light-emitting elements configured to store the video data.

### Claim 2 (depends on 1)

The pixel driving circuit of claim 1, wherein the first signal is to be input to a data input terminal of the pixel internal memory configured to store the stored data.

### Claim 3 (depends on 1)

The pixel driving circuit of claim 1, wherein the signal output from the signal detection circuit is to be input to a clock terminal of the pixel internal memory configured to receive a clock signal.

### Claim 4 (depends on 1)

The pixel driving circuit of claim 1, wherein the second signal output from the second low-pass filter is input to a reset terminal of the pixel internal memory configured to delete the stored data.

### Claim 5 (depends on 1)

The pixel driving circuit of claim 1, wherein the single flag memory cell is disposed farthest from a data input terminal of the pixel internal memory.

### Claim 6 (depends on 5)

The pixel driving circuit of claim 5,
wherein the pixel internal memory is configured to output the mode value stored in the single flag memory cell to the signal detection circuit, and
wherein the signal detection circuit is configured to output a column signal when the mode value corresponds to a first mode, and output a row signal when the mode value corresponds to a second mode.

### Claim 7 (depends on 1)

The pixel driving circuit of claim 1, further comprising:
K output switching elements connected to first ends of the K video data shift registers, respectively, to output the video data to respective corresponding light-emitting elements; and
K cycling switching elements connected between the first ends and second ends of each of the K video data shift registers to re-input the video data output from the first ends to the second ends, respectively.

### Claim 8 (depends on 7)

The pixel driving circuit of claim 7, wherein the K video data shift registers respectively further comprise a plurality of pulse width modulation (PWM) end memory cells configured to end PWM driving of each of the light-emitting elements.

### Claim 9 (depends on 8)

The pixel driving circuit of claim 8, wherein each of the PWM end memory cells is located adjacent to a least significant bit (LSB) of the video data of a corresponding light-emitting element.

### Claim 10 (depends on 1)

A pixel circuit comprising:
the pixel driving circuit of claim 1; and
a plurality of light-emitting elements.

### Claim 11 (depends on 10)

A display device comprising:
a display panel in which a plurality of pixel circuits, each being the pixel circuit of claim 10, are disposed;
a scan driving circuit configured to output a row signal through a plurality of scan lines connected to row signal input terminals of the pixel circuits disposed in a row direction; and
a data driving circuit configured output a column signal through a plurality of data lines connected to column signal input terminals of the pixel circuits disposed in a column direction,
wherein the column signal comprises a mode value data signal, a setting value data signal, and a video data signal.

### Claim 12 (depends on 11)

The display device of claim 11, wherein the row signal comprises a first scan signal for inputting to the pixel internal memory, a second scan signal for inputting setting value data related to the pixel driving data and the video data, and a clock signal for pulse width modulation (PWM) driving.

### Claim 13 (depends on 12)

The display device of claim 12, wherein the first scan signal has a frequency lower than the preset second cutoff frequency of the second low-pass filter.

### Claim 14 (depends on 12)

The display device of claim 12, wherein the second scan signal has a frequency lower than the preset first cutoff frequency of the first low-pass filter and higher than the preset second cutoff frequency of the second low-pass filter.

### Claim 15 (depends on 12)

The display device of claim 12, wherein the clock signal for PWM driving has a frequency higher than the preset first cutoff frequency of the first low-pass filter.

### Claim 16 (depends on 12)

The display device of claim 12, wherein the scan driving circuit is configured to output the row signal, in which M clock signals are repeated, after one of the second scan signal according to an M-cycling operation mode.

### Claim 17 (depends on 11)

The display device of claim 11, wherein a most significant bit (MSB) of data in the column signal is the mode value.

### Claim 18 (depends on 11)

The display device of claim 11, wherein the video data comprises L-bit gradation data corresponding to a gradation of each of the light-emitting elements and 1-bit data of “0” as pulse width modulation (PWM) end data.