# US 12,112,694 B2 · Pixel and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,112,694 B2 - Document ID: US12112694B2 - Status: Granted - Kind: B2 - Application number: 18/374,070 - Filed: 2023-09-28 - Published: 2024-01-25 - Granted: 2024-10-08 - Earliest claimed: 2022-02-17 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: Minjae Jeong; Jangmi Kang; Hyeongseok Kim; Junhyun Park; Mukyung Jeon - Web page: https://patentgrep.com/patent/US12112694B2 ## CPC - G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED] - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 2300/0426: Layout of electrodes and connections - G09G 2300/043: Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor - G09G 2300/0852: being a dynamic memory with more than one capacitor - G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes - G09G 2310/0251: Precharge or discharge of pixel before applying new pixel voltage - G09G 2310/0262: The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes - G09G 2310/061: for resetting or blanking - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/0233: Improving the luminance or brightness uniformity across the screen - G09G 2320/045: Compensation of drifts in the characteristics of light emitting or modulating elements - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A pixel includes a light emitting element, a first transistor including a first electrode electrically connected to a first voltage line which supplies a first driving voltage, a second electrode electrically connected to the light emitting element, and a gate electrode connected to a first node, a second transistor connected between the first node and a second node and including a gate electrode connected to a first scan line, a third transistor connected between the second electrode of the first transistor and the second node and including a gate electrode connected to a second scan line, and a booting capacitor connected between the second node and the second scan line. ## Claims ### Claim 1 A pixel comprising: a light emitting element; a first transistor including a first electrode electrically connected to a first voltage line which supplies a first driving voltage, a second electrode and a gate electrode connected to a first node; a second transistor connected between a data line and the first electrode of the first transistor, and including a gate electrode connected to a first scan line; and a sixth transistor connected between the second electrode of the first transistor and the light emitting element, and including a gate electrode connected to a second emission control line, wherein each of a plurality of frames includes a first cycle and a second cycle, wherein a first scan signal provided to the first scan line has an active level during a write period of the first cycle, wherein the first scan signal provided to the first scan line is maintained at an inactive level during the second cycle, and wherein one of a data signal and a bias signal is provided to the data line during the write period. ### Claim 2 (depends on 1) The pixel of claim 1, further comprising: a third transistor connected between the second electrode of the first transistor and the first node, and including a gate electrode connected to a second scan line; a fourth transistor connected between the first node and a first initialization voltage line, and including a gate electrode connected to a third scan line; a ninth transistor connected between the first electrode of the first transistor and a second node, and including a gate electrode connected to a fourth scan line; and a first capacitor connected between the first node and the second node. ### Claim 3 (depends on 2) The pixel of claim 2, wherein each of the first transistor, the second transistor, and the sixth transistor is a P-type transistor, and each of the third transistor, the fourth transistor and the ninth transistor is an N-type transistor. ### Claim 4 (depends on 2) The pixel of claim 2, further comprising: a seventh transistor connected between the light emitting element and a second initialization voltage line, and including a gate electrode connected to the first scan line; an eighth transistor connected between the first voltage line and the first electrode of the first transistor, and including a gate electrode connected to a first emission control line; and a second capacitor connected between the first voltage line and the second node. ### Claim 5 (depends on 4) The pixel of claim 4, wherein a second emission control signal provided to the second emission control line has inactive level during the write period of the first cycle, and wherein a first emission control signal provided to the first emission control line has inactive level during the write period of the first cycle. ### Claim 6 (depends on 4) The pixel of claim 4, wherein a second scan signal, a third scan signal and a fourth scan signal are provided to the second scan line, the third scan line and the fourth scan line, respectively, and wherein each of the second scan signal, the third scan signal and the fourth scan signal has the inactive level during the write period of the first cycle. ### Claim 7 A display device comprising: a display panel including a pixel; a driving controller which receives a control signal and an input image signal and outputs an output image signal, a first control signal, and a second control signal; a data driving circuit which outputs a data signal to the pixel in response to the output image signal and the first control signal; and a scan driving circuit which outputs a first scan signal to the pixel in response to the second control signal, wherein the pixel includes: a light emitting element; a first transistor including a first electrode electrically connected to a first voltage line which supplies a first driving voltage, a second electrode and a gate electrode connected to a first node; a second transistor connected between a data line and the first electrode of the first transistor, and including a gate electrode connected to a first scan line; and a sixth transistor connected between the second electrode of the first transistor and the light emitting element, and including a gate electrode connected to a second emission control line, wherein each of a plurality of frames includes a first cycle and a second cycle, wherein the first scan signal provided to the first scan line has an active level during a write period of the first cycle, wherein the first scan signal provided to the first scan line is maintained at an inactive level during the second cycle, and wherein one of a data signal and a bias signal is provided to the data line during the write period. ### Claim 8 (depends on 7) The display device of claim 7, the pixel further includes: a third transistor connected between the second electrode of the first transistor and the first node, and including a gate electrode connected to a second scan line; a fourth transistor connected between the first node and a first initialization voltage line, and including a gate electrode connected to a third scan line; a ninth transistor connected between the first electrode of the first transistor and a second node, and including a gate electrode connected to a fourth scan line; and a first capacitor connected between the first node and the second node. ### Claim 9 (depends on 8) The display device of claim 8, wherein each of the first transistor, the second transistor, and the sixth transistor is a P-type transistor, and each of the third transistor, the fourth transistor and the ninth transistor is an N-type transistor. ### Claim 10 (depends on 8) The display device of claim 8, the pixel further includes: a seventh transistor connected between the light emitting element and a second initialization voltage line, and including a gate electrode connected to the first scan line; an eighth transistor connected between the first voltage line and the first electrode of the first transistor, and including a gate electrode connected to a first emission control line; and a second capacitor connected between the first voltage line and the second node. ### Claim 11 (depends on 10) The display device of claim 10, wherein a second emission control signal provided to the second emission control line has inactive level during the write period of the first cycle, and wherein a first emission control signal provided to the first emission control line has inactive level during the write period of the first cycle. ### Claim 12 (depends on 11) The display device of claim 11, wherein the scan driving circuit further outputs a second scan signal, a third scan signal and a fourth scan signal in response to the second control signal, wherein the second scan signal, the third scan signal and the fourth scan signal are provided to the second scan line, the third scan line and the fourth scan line, respectively, and wherein each of the second scan signal, the third scan signal and the fourth scan signal has the inactive level during the write period of the first cycle. ### Claim 13 A pixel comprising: a light emitting element; a first transistor including a first electrode electrically connected to a first voltage line which supplies a first driving voltage, a second electrode and a gate electrode connected to a first node; a second transistor connected between a data line and the first electrode of the first transistor, and including a gate electrode connected to a first scan line; and a sixth transistor connected between the second electrode of the first transistor and the light emitting element, and including a gate electrode connected to a second emission control line, wherein each of a first frame and a second frame includes a first cycle and a second cycle, wherein a first scan signal provided to the first scan line has an active level during a data write period of the first cycle of the first frame and a bias period of the first cycle of the second frame, wherein the first scan signal provided to the first scan line is maintained at an inactive level during the second cycle of the first frame and the second cycle of the second frame, and wherein a data signal is provided to the data line during the data write period and a bias signal is provided to the data line during the bias period. ### Claim 14 (depends on 13) The pixel of claim 13, further comprising: a third transistor connected between the second electrode of the first transistor and the first node, and including a gate electrode connected to a second scan line; a fourth transistor connected between the first node and a first initialization voltage line, and including a gate electrode connected to a third scan line; a ninth transistor connected between the first electrode of the first transistor and a second node, and including a gate electrode connected to a fourth scan line; and a first capacitor connected between the first node and the second node. ### Claim 15 (depends on 14) The pixel of claim 14, wherein each of the first transistor, the second transistor, and the sixth transistor is a P-type transistor, and each of the third transistor, the fourth transistor and the ninth transistor is an N-type transistor. ### Claim 16 (depends on 14) The pixel of claim 14, further comprising: a seventh transistor connected between the light emitting element and a second initialization voltage line, and including a gate electrode connected to the first scan line; an eighth transistor connected between the first voltage line and the first electrode of the first transistor, and including a gate electrode connected to a first emission control line; and a second capacitor connected between the first voltage line and the second node. ### Claim 17 (depends on 16) The pixel of claim 16, wherein a second emission control signal provided to the second emission control line has inactive level during the data write period of the first cycle of the first frame and the bias period of the first cycle of the second frame, and wherein a first emission control signal provided to the first emission control line has inactive level during the data write period of the first cycle of the first frame and the bias period of the first cycle of the second frame. ### Claim 18 (depends on 16) The pixel of claim 16, wherein a second scan signal, a third scan signal and a fourth scan signal are provided to the second scan line, the third scan line and the fourth scan line, respectively, wherein each of the second scan signal, the third scan signal and the fourth scan signal has the inactive level during the second cycle of the first frame, and wherein each of the second scan signal, the third scan signal and the fourth scan signal has the inactive level during the second frame.