# US 12,112,692 B2 · Pixel drive circuit, driving method, and display panel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,112,692 B2 - Document ID: US12112692B2 - Status: Granted - Kind: B2 - Application number: 18/213,267 - Filed: 2023-06-23 - Published: 2024-05-09 - Granted: 2024-10-08 - Earliest claimed: 2022-11-09 - Assignees: Hkc Corporation Limited - Applicants: Hkc Corporation Limited - Inventors: Zeyao Li; Haoxuan Zheng - Web page: https://patentgrep.com/patent/US12112692B2 ## CPC - G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED] - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2300/0852: being a dynamic memory with more than one capacitor - G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes - G09G 2310/0262: The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes - G09G 2310/066: Waveforms comprising a gently increasing or decreasing portion, e.g. ramp - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/045: Compensation of drifts in the characteristics of light emitting or modulating elements - G09G 2320/0633: by amplitude modulation of the brightness of the illumination source - G09G 2320/064: by time modulation of the brightness of the illumination source - G09G 2330/021: Power management, e.g. power saving - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract Disclosed are a pixel drive circuit, a driving method, and a display panel. The pixel drive circuit includes a light-emitting element; a power supply line, including a high-potential power supply and a low-potential power supply, connected to the light-emitting element; a pulse amplitude modulation unit, including a first drive transistor connected to the light-emitting element and the power supply line; wherein a driving current with different amplitudes is provided to the light-emitting element according to a voltage applied to a gate of the first drive transistor; and a pulse width modulation unit, including a second drive transistor connected to the light-emitting element and the pulse amplitude modulation unit; wherein a duration of the driving current of the light-emitting element is controlled according to a voltage applied to a gate of the second drive transistor. ## Claims ### Claim 1 A pixel drive circuit, comprising: a light-emitting element; a power supply line, comprising a high-potential power supply and a low-potential power supply, connected to the light-emitting element; a pulse amplitude modulation unit, comprising a first drive transistor connected to the light-emitting element and the power supply line; wherein a driving current with different amplitudes is provided to the light-emitting element according to a voltage applied to a gate of the first drive transistor; and a pulse width modulation unit, comprising a second drive transistor connected to the light-emitting element and the pulse amplitude modulation unit; wherein a duration of the driving current of the light-emitting element is controlled according to a voltage applied to a gate of the second drive transistor; wherein the pulse width modulation unit further comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor; a first pole plate of the first capacitor is connected to the gate of the second drive transistor, and a second pole plate of the first capacitor is connected to the power supply line; a source of the first transistor is connected to a first signal line, a drain of the first transistor is connected to the gate of the second drive transistor, and a gate of the first transistor is connected to a first scan control line; a source of the second transistor is connected to a second signal line, a drain of the second transistor is connected to the gate of the second drive transistor, and a gate of the second transistor is connected to a drain of the third transistor and to a first pole plate of the second capacitor; a source of the third transistor is connected to a third signal line, the drain of the third transistor is connected to the gate of the second transistor and to the first pole plate of the second capacitor, and a gate of the third transistor is connected to a second scan control line; a source of the fourth transistor is connected to a control signal line, a drain of the fourth transistor is connected to a second pole plate of the second capacitor, and a gate of the fourth transistor is connected to a third scan control line. ### Claim 2 (depends on 1) The pixel drive circuit according to claim 1, wherein a source of the first drive transistor is connected to the power supply line, a drain of the first drive transistor is connected to a source of the second drive transistor, and a drain of the second drive transistor is connected to the light-emitting element. ### Claim 3 (depends on 1) The pixel drive circuit according to claim 1, further comprising a driving current detection unit connected to the drain of the first drive transistor and configured to detect a driving current of the first drive transistor; wherein the driving current detection unit comprises a first switch transistor; a source of the first switch transistor is connected to the drain of the first drive transistor, a drain of the first switch transistor is connected to a measurement line, and a gate of the first switch transistor is connected to a scan control line. ### Claim 4 (depends on 1) The pixel drive circuit according to claim 1, wherein the pulse width modulation unit further comprises a fifth transistor connected in parallel with the first transistor to control a gate voltage of the second drive transistor; wherein a source of the fifth transistor is connected to the first signal line, a drain of the fifth transistor is connected to the gate of the second drive transistor, and a gate of the fifth transistor is connected to the second scan control line, for maintaining an initial voltage of the gate of the second drive transistor. ### Claim 5 (depends on 1) The pixel drive circuit according to claim 1, further comprising a control unit connected to the light-emitting element and the power supply line, for controlling connection or disconnection of the light-emitting element; wherein the control unit comprises a second switch transistor; a source of the second switch transistor is connected to the drain of the second drive transistor, a drain of the second switch transistor is connected to the light-emitting element, and a gate of the second switch transistor is connected to a fourth scan control line. ### Claim 6 (depends on 1) The pixel drive circuit according to claim 1, wherein the pulse amplitude modulation unit further comprises a sixth transistor and a third capacitor; a source of the sixth transistor is connected to a data line, a drain of the sixth transistor is connected to a gate of the first drive transistor and to a first pole plate of the third capacitor, and a gate of the sixth transistor is connected to the first scan control line; a second pole plate of the second capacitor is connected to the power supply line. ### Claim 7 (depends on 1) The pixel drive circuit according to claim 1, wherein each of the first drive transistor, second drive transistor, first transistor, second transistor, third transistor, and fourth transistor is an N-type transistor or a P-type transistor. ### Claim 8 (depends on 1) A driving method of the pixel drive circuit according to claim 1; wherein the pulse amplitude modulation unit further comprises a sixth transistor and a third capacitor; a source of the sixth transistor is connected to a data line, a drain of the sixth transistor is connected to a gate of the first drive transistor and to a first pole plate of the third capacitor, and a gate of the sixth transistor is connected to the first scan control line; a second pole plate of the second capacitor is connected to the power supply line; the driving method comprises: a first stage, comprising: controlling, via the first scan control line of an Nth row, the sixth transistor and the first transistor to be turned on; transmitting a data voltage of the data line through the sixth transistor to the first pole plate of the third capacitor and the gate of the first drive transistor; maintaining the data voltage through the third capacitor to achieve an amplitude setting of a driving current of the first drive transistor; transmitting a first voltage of the first signal line through the first transistor to the gate of the second drive transistor and to the first pole plate of the first capacitor; and maintaining the first voltage through the first capacitor to keep the second drive transistor in a turned-off state; a second stage, comprising: controlling, via the second scan control line of an Nth row, the third transistor to be turned on; transmitting a third voltage of the third signal line through the third transistor to the gate of the second transistor and the first pole plate of the second capacitor, to keep the second transistor turned off; controlling, via the third scan control line, the fourth transistor to be turned on; and writing a first level voltage of the control signal line to the second pole plate of the second capacitor through the fourth transistor and transmitted to the gate of the second transistor through a coupling effect of the second capacitor; a third stage, comprising: controlling, via the third scan control line of an Nth row, the fourth transistor to be turned on; writing a second level voltage of the control signal line to the second pole plate of the second capacitor through the fourth transistor; and transmitting the second level voltage of the control signal line to the gate of the second transistor through the coupling effect of the second capacitor, to turn off the second transistor; a fourth stage, comprising: controlling, via the third scan control lines of all rows, the fourth transistor to be turned on; transmitting a swing voltage of the control signal line through the fourth transistor to the gate of the second transistor to control the second transistor to be turned on; and transmitting a second voltage of the second signal line through the second transistor to the gate of the second drive transistor to control the second drive transistor to be turned on; and controlling a turned-on time of the second transistor through the swing voltage, and controlling a turned-on time of the second drive transistor, thereby controlling a light-emitting time of the light emitting element. ### Claim 9 (depends on 8) The driving method according to claim 8, wherein the second transistor is a P-type transistor, and the swing voltage is a uniformly falling voltage; the light-emitting time is related to a decreasing slope of the swing voltage. ### Claim 10 (depends on 8) The driving method according to claim 8, wherein the second transistor is an N-type transistor, and the swing voltage is a uniformly rising voltage. ### Claim 11 (depends on 8) The driving method according to claim 8, wherein the second or third stage further comprises: controlling, via the scan control line of the Nth row, the first switching transistor to be turned on, for causing the drain of the first drive transistor to form a path with a measurement line and measuring the driving current of the first drive transistor. ### Claim 12 (depends on 11) The driving method according to claim 11, wherein the scan control line is the second scan control line or the third scan control line. ### Claim 13 (depends on 8) The driving method according to claim 8, wherein the pulse width modulation unit further comprises a fifth transistor; a source of the fifth transistor is connected to the first signal line, a drain of the fifth transistor is connected to the gate of the second drive transistor, and a gate of the fifth transistor is connected to the second scan control line; wherein the second stage further comprises: controlling, via the second scan control line of the Nth row, the fifth transistor to be turned on; and transmitting the first voltage of the first signal line to the first pole plate of the first capacitor and to the gate of the second drive transistor, for keeping a gate voltage of the second drive transistor constant. ### Claim 14 (depends on 8) The driving method according to claim 8, wherein the pixel drive circuit further comprises a control unit, the control unit comprising a second switch transistor; a source of the second switch transistor is connected to the drain of the second drive transistor, a drain of the second switch transistor is connected to the light-emitting element, and a gate of the second switch transistor is connected to a fourth scan control line; wherein the fourth stage further comprises: controlling, via the fourth scan control line, the second switch transistor to be turned on, for enabling the power supply line to form a path with the light-emitting element and causing the light-emitting element to emit light. ### Claim 15 A display panel, comprising a plurality of pixel cells arranged in an array; wherein each pixel cell is arranged with a pixel drive circuit; wherein the pixel drive circuit comprises: a light-emitting element; a power supply line, comprising a high-potential power supply and a low-potential power supply, connected to the light-emitting element; a pulse amplitude modulation unit, comprising a first drive transistor connected to the light-emitting element and the power supply line; wherein a driving current with different amplitudes is provided to the light-emitting element according to a voltage applied to a gate of the first drive transistor; and a pulse width modulation unit, comprising a second drive transistor connected to the light-emitting element and the pulse amplitude modulation unit; wherein a duration of the driving current of the light-emitting element is controlled according to a voltage applied to a gate of the second drive transistor; wherein the pulse width modulation unit further comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor; a first pole plate of the first capacitor is connected to the gate of the second drive transistor, and a second pole plate of the first capacitor is connected to the power supply line; a source of the first transistor is connected to a first signal line, a drain of the first transistor is connected to the gate of the second drive transistor, and a gate of the first transistor is connected to a first scan control line; a source of the second transistor is connected to a second signal line, a drain of the second transistor is connected to the gate of the second drive transistor, and a gate of the second transistor is connected to a drain of the third transistor and to a first pole plate of the second capacitor; a source of the third transistor is connected to a third signal line, the drain of the third transistor is connected to the gate of the second transistor and to the first pole plate of the second capacitor, and a gate of the third transistor is connected to a second scan control line; a source of the fourth transistor is connected to a control signal line, a drain of the fourth transistor is connected to a second pole plate of the second capacitor, and a gate of the fourth transistor is connected to a third scan control line. ### Claim 16 (depends on 15) The display panel according to claim 15, wherein a source of the first drive transistor is connected to the power supply line, a drain of the first drive transistor is connected to a source of the second drive transistor, and a drain of the second drive transistor is connected to the light-emitting element. ### Claim 17 (depends on 15) The display panel according to claim 15, wherein the pixel drive circuit further comprises a driving current detection unit connected to the drain of the first drive transistor and configured to detect a driving current of the first drive transistor; wherein the driving current detection unit comprises a first switch transistor; a source of the first switch transistor is connected to the drain of the first drive transistor, a drain of the first switch transistor is connected to a measurement line, and a gate of the first switch transistor is connected to a scan control line. ### Claim 18 (depends on 15) The display panel according to claim 15, wherein the pulse width modulation unit further comprises a fifth transistor connected in parallel with the first transistor to control a gate voltage of the second drive transistor; wherein a source of the fifth transistor is connected to the first signal line, a drain of the fifth transistor is connected to the gate of the second drive transistor, and a gate of the fifth transistor is connected to the second scan control line, for maintaining an initial voltage of the gate of the second drive transistor. ### Claim 19 (depends on 15) The display panel according to claim 15, wherein the pixel drive circuit further comprises a control unit connected to the light-emitting element and the power supply line, for controlling connection or disconnection of the light-emitting element; wherein the control unit comprises a second switch transistor; a source of the second switch transistor is connected to the drain of the second drive transistor, a drain of the second switch transistor is connected to the light-emitting element, and a gate of the second switch transistor is connected to a fourth scan control line. ### Claim 20 (depends on 15) The display panel according to claim 15, wherein the pulse amplitude modulation unit further comprises a sixth transistor and a third capacitor; a source of the sixth transistor is connected to a data line, a drain of the sixth transistor is connected to a gate of the first drive transistor and to a first pole plate of the third capacitor, and a gate of the sixth transistor is connected to the first scan control line; a second pole plate of the second capacitor is connected to the power supply line.