# US 12,112,673 B2 · Display panel and display device

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- Number: US 12,112,673 B2
- Document ID: US12112673B2
- Status: Granted
- Kind: B2
- Application number: 17/796,660
- Filed: 2021-06-10
- Published: 2023-10-19
- Granted: 2024-10-08
- Earliest claimed: 2020-07-31
- Assignees: Beijing Boe Display Technology Co., Ltd.; Boe Technology Group Co., Ltd.
- Applicants: Beijing BOE Display Technology Co., Ltd.; Boe Technology Group Co., Ltd.
- Inventors: Chongyang Zhao; Yingmeng Miao; Zhihua Sun; Feng Qu; Xiaochun Xu
- Web page: https://patentgrep.com/patent/US12112673B2

## CPC

- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 3/3266: Details of drivers for scan electrodes
- G09G 3/3677: {suitable for active matrices only}
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G09G 2300/0408: Integration of the drivers onto the display substrate
- G09G 2310/0202: Addressing of scan or signal lines
- G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present disclosure provides a display panel and a display device. The display panel includes p pixel unit groups, and each of the p pixel unit groups includes q rows of pixel units, both p and q being integers greater than or equal to 2. Pixel units in a same group are simultaneously supplied with a gate scan signal by a same shift register, and pixel units in a same group and in a same column are supplied with data voltage signals through different data lines, respectively.

## Claims

### Claim 1

A display panel, comprising p pixel unit groups, each of the p pixel unit groups comprising q rows of pixel units, both p and q being integers greater than or equal to 2; wherein pixel units in a same group are simultaneously supplied with a gate scan signal by a same shift register; and pixel units in a same group and in a same column are supplied with data voltage signals through different data lines, respectively;
the display panel further comprises N clock signal lines, N being an even number greater than or equal to 4, and p being greater than or equal to 2N; wherein each shift register is connected to one of the N clock signal lines, shift registers connected to different clock signal lines are different, and the q rows of pixel units in each group are adjacent to each other;
wherein pixel units in a same row are connected to a same gate line; each shift register comprises q shift register units, and the shift register units are connected to gate lines in one-to-one correspondence; and
wherein each shift register unit comprises a cascade signal output terminal and a signal output terminal, a signal output by the cascade signal output terminal and a signal output by the signal output terminal are the same as each other and are synchronous, the cascade signal output terminal is configured to be connected to a pull-up reset signal terminal of a shift register unit in a previous stage and a signal input terminal of a shift register unit in a next stage, and the signal output terminal is configured to be connected to a corresponding gate line.

### Claim 2 (depends on 1)

The display panel of claim 1, wherein each shift register unit is connected to one of the N clock signal lines through one signal connection line, and different shift register units are connected with different signal connection lines; or
wherein the q shift register units in each shift register are connected to a corresponding clock signal line through a same signal connection line, and a plurality of shift register units in different shift registers are connected with different signal connection lines, respectively.

### Claim 3 (depends on 1)

The display panel of claim 1, wherein each shift register unit comprises at least an input sub-circuit, an output sub-circuit, and a pull-up reset sub-circuit; wherein the input sub-circuit inputs, in response to an input signal input from a signal input terminal, the input signal to a pull-up node; the output sub-circuit outputs a clock signal input by a corresponding clock signal line through a signal output terminal in response to a potential of the pull-up node; and the pull-up reset sub-circuit resets the potential of the pull-up node through a turn-off level signal in response to a pull-up reset signal input from a pull-up reset signal terminal; and
every adjacent N shift registers are connected to the N clock signal lines in one-to-one correspondence, and an i-th shift register and an (i+N)-th shift register are connected to a same clock signal line, where i takes 1 to p−N.

### Claim 4 (depends on 3)

The display panel of claim 3, wherein in a case where a duty ratio of the clock signal is 30%, and N is an even number greater than or equal to 6,
a signal input terminal of each shift register unit in first to (N−4)/2 shift registers responds to a frame start signal;
a signal output terminal of a j-th shift register unit in an M-th shift register is connected to a signal input terminal of a j-th shift register unit in an [M+(N−4)/2]-th shift register; and
a pull-up reset signal terminal of a j-th shift register unit in an L-th shift register is connected to a signal output terminal of a j-th shift register unit in an [L+(N/2−1)]-th shift register; where M takes 1 to p−(N−4)/2; L takes 1 to p−(N/2−1); and j takes 1 to q.

### Claim 5 (depends on 4)

The display panel of claim 4, further comprising N−2 redundant shift registers, wherein the N−2 redundant shift registers are connected to N−2 clock signal lines, respectively, and each redundant shift register comprises q redundant shift register units; each redundant shift register unit has the same structure as each shift register unit; wherein
signal output terminals of j-th redundant shift register units in first to (N/2−1)-th redundant shift registers are connected to pull-up reset signal terminals of j-th shift register units in [p−(N/2−2)]-th to p-th shift registers, respectively; and
signal output terminals of j-th redundant shift register units in N/2-th to (N−2)-th redundant shift registers are connected to pull-up reset signal terminals of the j-th redundant shift register units in the first to (N/2−1)-th redundant shift registers, respectively.

### Claim 6 (depends on 3)

The display panel of claim 3, wherein in a case where a duty ratio of the clock signal is 40%, and N is an even number greater than or equal to 4;
a signal input terminal of each shift register unit in first to (N−2)/2 shift registers responds to a frame start signal;
a signal output terminal of a j-th shift register unit in an M-th shift register is connected to a signal input terminal of a j-th shift register unit in an [M+(N−2)/2]-th shift register; and
a pull-up reset signal terminal of a j-th shift register unit in an L-th shift register is connected to a signal output terminal of a j-th shift register unit in an (L+N/2)-th shift register; where M takes 1 to p−(N−2)/2; L takes 1 to p−N/2; and j takes 1 to q.

### Claim 7 (depends on 6)

The display panel of claim 6, further comprising N redundant shift registers, wherein the N redundant shift registers are connected to the N clock signal lines, respectively; each redundant shift register comprises q redundant shift register units; each redundant shift register unit has the same structure as each shift register unit; wherein
signal output terminals of j-th redundant shift register units in first to (N/2)-th redundant shift registers are connected to pull-up reset signal terminals of j-th shift register units in (p−N/2+1)-th to p-th shift registers, respectively; and signal output terminals of j-th redundant shift register units in (N/2+1)-th to N-th redundant shift registers are connected to pull-up reset signal terminals of the j-th redundant shift register units in the first to (N/2)-th redundant shift registers, respectively.

### Claim 8 (depends on 3)

The display panel of claim 3, wherein in a case where a duty ratio of the clock signal is 50%, and N is an even number greater than or equal to 4;
a signal input terminal of each shift register unit in first to N/2 shift registers responds to a frame start signal;
a signal output terminal of a j-th shift register unit in an M-th shift register is connected to a signal input terminal of a j-th shift register unit in an (M+N/2)-th shift register; and
a pull-up reset signal terminal of a j-th shift register unit in an L-th shift register is connected to a signal output terminal of a j-th shift register unit in an [L+(N/2+1)]-th shift register; where M takes 1 to p−N/2; L takes 1 to p−(N/2+1); and j takes 1 to q.

### Claim 9 (depends on 8)

The display panel of claim 8, further comprising N+2 redundant shift registers, wherein first to N-th redundant shift registers of the N+2 redundant shift registers are connected to the N clock signal lines, respectively, and (N+1)-th and (N+2)-th redundant shift registers of the N+2 redundant shift registers are connected to first and second clock signal lines, respectively; each of the N redundant shift registers comprises q redundant shift register units; each redundant shift register unit has the same structure as each shift register unit; wherein
signal output terminals of j-th redundant shift register units in first to (N/2+1)-th redundant shift registers are connected to pull-up reset signal terminals of j-th shift register units in (p−N/2)-th to p-th shift registers, respectively; and
signal output terminals of j-th redundant shift register units in (N/2+2)-th to (N+2)-th redundant shift registers are connected to pull-up reset signal terminals of the j-th redundant shift register units in the first to (N/2+1)-th redundant shift registers, respectively.

### Claim 10 (depends on 1)

The display panel of claim 1, wherein pixel units in a same row are connected to a same gate line; each shift register comprises one shift register unit and q sub signal output terminals connected to a signal output terminal of the shift register unit, and the sub signal output terminals are connected to gate lines in one-to-one correspondence.

### Claim 11 (depends on 10)

The display panel of claim 10, wherein each shift register unit comprises at least an input sub-circuit, an output sub-circuit, and a pull-up reset sub-circuit; wherein the input sub-circuit inputs, in response to an input signal input from a signal input terminal, the input signal to a pull-up node; the output sub-circuit inputs a clock signal input through a corresponding clock signal line to a signal output terminal in response to a potential of the pull-up node, so that the signal output terminal outputs the clock signal through the q sub signal output terminals; the pull-up reset sub-circuit resets the potential of the pull-up node through a turn-off level signal in response to a pull-up reset signal input from a pull-up reset signal terminal; and
every adjacent N shift register units are connected to the N clock signal lines in one-to-one correspondence, and an i-th shift register unit and an (i+N)-th shift register unit are connected to a same clock signal line, where i takes 1 to p−N.

### Claim 12 (depends on 11)

The display panel of claim 11, wherein in a case where a duty ratio of the clock signal is 30%, and N is an even number greater than or equal to 6,
signal input terminals of first to (N−4)/2 shift register units respond to a frame start signal;
a signal output terminal of an M-th shift register unit is connected to a signal input terminal of an [M+(N−4)/2]-th shift register unit; and
a pull-up reset signal terminal of an L-th shift register unit is connected to a signal output terminal of an [L+(N/2−1)]-th shift register unit; where M takes 1 to p−(N−4)/2; and L takes 1 to p−(N/2−1).

### Claim 13 (depends on 12)

The display panel of claim 12, further comprising N−2 redundant shift registers, wherein the N−2 redundant shift registers are connected to N−2 clock signal lines, respectively, and each redundant shift register comprises one redundant shift register unit; the redundant shift register unit has the same structure as the shift register unit; wherein
signal output terminals of first to (N/2−1)-th redundant shift register units are connected to pull-up reset signal terminals of [p−(N/2−2)]-th to p-th shift register units, respectively; and
signal output terminals of N/2-th to (N−2)-th redundant shift register units are connected to pull-up reset signal terminals of the first to (N/2−1)-th redundant shift register units, respectively.

### Claim 14 (depends on 11)

The display panel of claim 11, wherein in a case where a duty ratio of the clock signal is 40%, and N is an even number greater than or equal to 4;
signal input terminals of first to (N−2)/2 shift register units responds to a frame start signal;
a signal output terminal of an M-th shift register unit is connected to a signal input terminal of an [M+(N−2)/2]-th shift register unit; and
a pull-up reset signal terminal of an L-th shift register unit is connected to a signal output terminal of an (L+N/2)-th shift register unit; where M takes 1 to p−(N−2)/2; and L takes 1 to p−N/2.

### Claim 15 (depends on 14)

The display panel of claim 14, further comprising N redundant shift registers, wherein the N redundant shift registers are connected to the N clock signal lines, respectively; each redundant shift register comprises one redundant shift register unit; each redundant shift register unit has the same structure as each shift register unit; wherein
signal output terminals of first to (N/2)-th redundant shift register units are connected to pull-up reset signal terminals of (p−N/2+1)-th to p-th shift register units, respectively; and
signal output terminals of (N/2+1)-th to N-th redundant shift register units are connected to pull-up reset signal terminals of the first to (N/2)-th redundant shift register units, respectively.

### Claim 16 (depends on 11)

The display panel of claim 11, wherein in a case where a duty ratio of the clock signal is 50%, and N is an even number greater than or equal to 4;
signal input terminals of first to N/2 shift register units responds to a frame start signal;
a signal output terminal of an M-th shift register unit is connected to a signal input terminal of an (M+N/2)-th shift register unit; and
a pull-up reset signal terminal of an L-th shift register unit is connected to a signal output terminal of an [L+(N/2+1)]-th shift register unit; where M takes 1 to p−N/2; and L takes 1 to p−(N/2+1).

### Claim 17 (depends on 16)

The display panel of claim 16, further comprising N+2 redundant shift registers, wherein first to N-th redundant shift registers of the N+2 redundant shift registers are connected to the N clock signal lines, respectively, and (N+1)-th and (N+2)-th redundant shift registers of the N+2 redundant shift registers are connected to first and second clock signal lines, respectively; each redundant shift register comprises one redundant shift register unit; each redundant shift register unit has the same structure as each shift register unit; wherein
signal output terminals of first to (N/2+1)-th redundant shift register units are connected to pull-up reset signal terminals of (p−N/2)-th to p-th shift register units, respectively; and
signal output terminals of (N/2+2)-th to (N+2)-th redundant shift register units are connected to pull-up reset signal terminals of the first to (N/2+1)-th redundant shift register units, respectively.

### Claim 18 (depends on 1)

A display device, comprising the display panel of claim 1.