# US 12,112,667 B2 · Pixel and display apparatus capable of controlling test function preliminary class > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,112,667 B2 - Document ID: US12112667B2 - Status: Granted - Kind: B2 - Application number: 18/366,257 - Filed: 2023-08-07 - Published: 2024-02-15 - Granted: 2024-10-08 - Earliest claimed: 2022-08-12 - Assignees: Sapien Semiconductors Inc. - Applicants: Sapien Semiconductors Inc. - Inventors: Ji Han Kim; Sung Ho Hwang; Ji Haeng Lee; Dae Young Jung - Web page: https://patentgrep.com/patent/US12112667B2 ## CPC - G09G 3/006: {Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309)} - G09G 3/2085: {Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination} - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2330/12: Test circuits or failure detection circuits included in a display system, as permanent part thereof - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A pixel driving circuit includes a memory unit storing data based on a first signal and a second signal, a driver connected to a luminous element and supplying electric power to the luminous element based on the data stored in the memory unit, and a test controller controlling entry into a test mode in which it is tested whether the pixel driving circuit is defective, wherein the test controller generates a test mode activation signal based on the first signal and the second signal. ## Claims ### Claim 1 A pixel driving circuit comprising: a memory storing data based on a first signal and a second signal; a driver connected to a luminous element and supplying electric power to the luminous element based on the data stored in the memory; and a test controller controlling entry into a test mode in which it is tested whether the pixel driving circuit is defective, wherein the test controller receives the first signal and the second signal and generates a test mode activation signal based on the first signal and the second signal, wherein the pixel driving circuit is included in each individual pixel and is configured to drive the individual pixel based on the first signal and the second signal. ### Claim 2 (depends on 1) The pixel driving circuit of claim 1, wherein the memory stores the data by using the first signal as a clock signal, and the test controller generates the test mode activation signal by using the second signal as a clock signal. ### Claim 3 (depends on 2) The pixel driving circuit of claim 2, wherein the test controller generates the test mode activation signal based on a falling edge of the second signal. ### Claim 4 (depends on 2) The pixel driving circuit of claim 2, wherein the test controller comprises a D flipflop having a data signal input terminal to which the first signal is input and a clock signal input terminal to which an inverted signal of the second signal is input. ### Claim 5 (depends on 4) The pixel driving circuit of claim 4, wherein the test controller comprises a plurality of D flipflops that are connected to one another in series, the inverted signal of the second signal is input to the clock signal input terminal in each of the plurality of D flipflops, the first signal is input to the data signal input terminal of a frontmost D flipflop from among the plurality of D flipflops, and an output from an adjacent D flipflop is input to the data signal input terminal of the D flipflop other than the frontmost D flipflop, from among the plurality of D flipflops. ### Claim 6 (depends on 5) The pixel driving circuit of claim 5, wherein the test controller further comprises an OR gate to which an output from the frontmost D flipflop from among the plurality of D flipflops and an output from a rearmost D flipflop from among the plurality of D flipflops are input. ### Claim 7 (depends on 1) The pixel driving circuit of claim 1, wherein, when the test mode activation signal is in a logic high, input of the data to the memory is blocked based on the first signal and the second signal. ### Claim 8 (depends on 7) The pixel driving circuit of claim 7, further comprising a controller controlling operations of the driver, wherein the controller generates a test control signal based on the test mode activation signal from the test controller. ### Claim 9 (depends on 8) The pixel driving circuit of claim 8, wherein, when the test control signal is in a logic high, it is tested whether the driver and the luminous element are defective. ### Claim 10 (depends on 8) The pixel driving circuit of claim 8, wherein, when the test control signal is in a logic high, a current does not flow in the driver and whether the luminous element is defective is tested. ### Claim 11 A display apparatus comprising: a display panel including an arrangement of a plurality of pixel driving circuits forming rows and columns; a scan driving circuit outputting a first signal sequentially to the plurality of pixel driving circuits arranged in a row direction, from among the plurality of pixel driving circuits included in the display panel; and a data driving circuit outputting to the plurality of pixel driving circuits arranged in a column direction, from among the plurality of pixel driving circuits included in the display panel, a second signal related to a driving of luminous elements corresponding respectively to the plurality of pixel driving circuits, wherein each of the plurality of pixel driving circuits comprises: a memory storing data based on the first signal and the second signal; a driver connected to a luminous element and supplying electric power to the luminous element based on the data stored in the memory; and a test controller controlling entry into a test mode in which it is tested whether the pixel driving circuit is defective, wherein the test controller receives the first signal and the second signal and generates a test mode activation signal based on the first signal and the second signal wherein the pixel driving circuit is included in each individual pixel and is configured to drive the individual pixel according to the first signal and the second signal.