# US 12,112,398 B2 · Disaggregation of system-on-chip (SOC) architecture

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- Number: US 12,112,398 B2
- Document ID: US12112398B2
- Status: Granted
- Kind: B2
- Application number: 18/470,652
- Filed: 2023-09-20
- Published: 2024-01-11
- Granted: 2024-10-08
- Earliest claimed: 2019-03-15
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Naveen Matam; Lance Cheney; Eric Finley; Varghese George; Sanjeev Jahagirdar; Altug Koker; Josh Mastronarde; Iqbal Rajwani; Lakshminarayanan Striramassarma; Melaku Teshome; Vikranth Vemulapalli; Binoj Xavier
- Web page: https://patentgrep.com/patent/US12112398B2

## CPC

- G06F 13/4068: {Electrical coupling}
- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)}
- G06F 13/409: {Mechanical coupling (back panels H05K7/1438)}
- H10W 90/00: Package configurations
- H10W 70/63: Vias, e.g. via plugs
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

## Claims

### Claim 1

An apparatus comprising:
a package assembly including:
a first base chiplet comprising:
a first interconnect fabric, and
a first plurality of cache banks coupled to or integrated with the first interconnect fabric;
a first logic chiplet stacked on the first base chiplet, the first logic chiplet comprising:
a cluster of compute units to perform parallel execution of compute shader instructions or graphics shader instructions;
a first interconnect structure to couple the cluster of compute units to the first interconnect fabric;
a second base chiplet coupled to the first base chiplet by a second interconnect structure, the second base chiplet comprising:
a second interconnect fabric, and
a second plurality of cache banks coupled to or integrated with the second interconnect fabric;
a second logic chiplet stacked on the second base chiplet, the second logic chiplet comprising:
a plurality of application processor cores to execute instructions; and
a third interconnect structure to couple the second logic chiplet to the second interconnect fabric,
wherein the first logic chiplet is manufactured using a different process technology than that used to manufacture the first and second base chiplets.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein at least one of the first and second base chiplets further comprise:
a fourth interconnect structure to couple the at least one of the first and second base chiplets to a memory.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the cluster of compute units and the plurality of application processor cores are to access the memory through the first and second base chiplets, respectively.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the memory comprises a high-bandwidth memory (HBM).

### Claim 5 (depends on 1)

The apparatus of claim 1, further comprising:
a package substrate coupled to the first and second base chiplets, and
a package interconnect to electrically couple the package substrate to one or more devices.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein at least one of the first and second base chiplets further comprise:
a microcontroller to execute firmware to perform power management operations.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the power management operations comprise controlling a voltage and frequency of at least one of the first and second base chiplets and the first and second logic chiplets.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the voltage and frequency are to be independently controlled for the at least one of the first and second base chiplets and the first and second logic chiplets.

### Claim 9 (depends on 7)

The apparatus of claim 7, wherein each chiplet of the first and second base chiplets and the first and second logic chiplets comprises a separate power domain and clock domain.

### Claim 10

A graphics processing system comprising:
a package assembly including:
a first base chiplet comprising:
a first interconnect fabric, and
a first plurality of cache banks coupled to or integrated with the first interconnect fabric;
a first logic chiplet stacked on the first base chiplet, the first logic chiplet comprising:
a cluster of compute units to perform parallel execution of compute shader instructions or graphics shader instructions;
a first interconnect structure to couple the cluster of compute units to the first interconnect fabric;
a second base chiplet coupled to the first base chiplet by a second interconnect structure, the second base chiplet comprising:
a second interconnect fabric, and
a second plurality of cache banks coupled to or integrated with the second interconnect fabric;
a second logic chiplet stacked on the second base chiplet, the second logic chiplet comprising:
a plurality of application processor cores to execute instructions; and
a third interconnect structure to couple the second logic chiplet to the second interconnect fabric,
wherein the first logic chiplet is manufactured using a different process technology than that used to manufacture the first and second base chiplets,
wherein at least one of the first and second base chiplets further comprise a fourth interconnect structure to couple the at least one of the first and second base chiplets to a memory, and
wherein the cluster of compute units and the plurality of application processor cores are to access the memory through the first and second base chiplets, respectively.

### Claim 11 (depends on 10)

The graphics processing system of claim 10 wherein the memory comprises a high-bandwidth memory (HBM).

### Claim 12 (depends on 10)

The graphics processing system of claim 10 further comprising:
a package substrate coupled to the first and second base chiplets, and
a package interconnect to electrically couple the package substrate to one or more devices.

### Claim 13 (depends on 10)

The graphics processing system of claim 10, wherein at least one of the first and second base chiplets further comprise:
a microcontroller to execute firmware to perform power management operations.

### Claim 14 (depends on 13)

The graphics processing system of claim 13, wherein the power management operations comprise controlling a voltage and frequency of at least one of the first and second base chiplets and the first and second logic chiplets.

### Claim 15 (depends on 14)

The graphics processing system of claim 14, wherein the voltage and frequency are to be independently controlled for the at least one of the first and second base chiplets and the first and second logic chiplets.

### Claim 16 (depends on 14)

The graphics processing system of claim 14, wherein each chiplet of the first and second base chiplets and the first and second logic chiplets comprises a separate power domain and clock domain.

### Claim 17

A method of assembling an apparatus including a plurality of chiplets, the method comprising:
assembling a package assembly including a first base chiplet comprising a first interconnect fabric and a first plurality of cache banks coupled to or integrated with the first interconnect fabric;
stacking a first logic chiplet on the first base chiplet, the first logic chiplet comprising a cluster of compute units to perform parallel execution of compute shader instructions or graphics shader instructions;
coupling the cluster of compute units to the first interconnect fabric via a first interconnect structure;
coupling the first base chiplet to a second base chiplet by a second interconnect structure, the second base chiplet comprising a second interconnect fabric and a second plurality of cache banks coupled to or integrated with the second interconnect fabric;
stacking a second logic chiplet on the second base chiplet, the second logic chiplet comprising a plurality of application processor cores to execute instructions; and
coupling the second logic chiplet to the second interconnect fabric via a third interconnect structure, wherein the first logic chiplet is manufactured using a different process technology than that used to manufacture the first base chiplet and the second base chiplet.

### Claim 18 (depends on 17)

The method of claim 17, further comprising coupling the at least one of the first and second base chiplets to a memory via a fourth interconnect structure and enabling the cluster of compute units and the plurality of application processor cores to access the memory through the first and second base chiplets, respectively, wherein the memory comprises a high-bandwidth memory (HBM).

### Claim 19 (depends on 18)

The method of claim 18, further comprising coupling a package substrate to the first and second base chiplets and electrically coupling the package substrate to one or more devices via a package interconnect.

### Claim 20 (depends on 17)

The method of claim 17, further comprising configuring a microcontroller of at least one of the first and second base chiplets to execute firmware to perform power management operations, the power management operations comprising controlling a voltage and frequency of at least one of the first and second base chiplets and the first and second logic chiplets.