Task execution in a SIMD processing unit with parallel groups of processing lanes

A method of using a single instruction multiple data (SIMD) processing unit to process a plurality of work items, wherein the work items are arranged for executing a common sequence of instructions on respective pixels of a pixel quad, wherein the SIMD processing unit comprises a group of processing lanes, each processing lane in the group being configured to execute instructions of a respective block of work items over a plurality of processing cycles, the method comprising:

• executing instructions of work items using the group of processing lanes;
• and
• causing the group of processing lanes to skip a particular processing cycle in response to making a determination that there are no valid work items scheduled for execution over the group of processing lanes in the particular processing cycle.

A non-transitory computer readable storage medium having stored thereon an integrated circuit dataset description that when inputted causes an integrated circuit manufacturing system to generate a single instruction multiple data (SIMD) processing unit configured to process a plurality of work items, wherein the work items are arranged for executing a common sequence of instructions on respective pixels of a pixel quad, the SIMD processing unit comprising:

• a group of processing lanes, each processing lane in the group being configured to execute instructions of a respective block of work items over a plurality of processing cycles;
• and
• logic configured to cause the group of processing lanes to skip a particular processing cycle in response to making a determination that there are no valid work items scheduled for execution over the group of processing lanes in the particular processing cycle.