# US 12,112,258 B2 · Neuromorphic operations using posits

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- Number: US 12,112,258 B2
- Document ID: US12112258B2
- Status: Granted
- Kind: B2
- Application number: 18/131,949
- Filed: 2023-04-07
- Published: 2023-08-03
- Granted: 2024-10-08
- Earliest claimed: 2020-06-29
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Vijay S. Ramesh; Richard C. Murphy
- Web page: https://patentgrep.com/patent/US12112258B2

## CPC

- G06N 3/065: Analogue means
- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G06F 7/48: using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06N 3/049: Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
- G06N 3/088: Non-supervised learning, e.g. competitive learning
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 7/16: Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
- G11C 11/4063: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- H03M 1/12: Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence)
- H03M 1/66: Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence)
- G06N 3/048: Activation functions
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

Systems, apparatuses, and methods related to a neuron built with posits are described. An example system may include a memory device and the memory device may include a plurality of memory cells. The plurality of memory cells can store data including a bit string in an analog format. A neuromorphic operation can be performed on the data in the analog format. The example system may include an analog to digital converter coupled to the memory device. The analog to digital converter may convert the bit string in the analog format stored in at least one of the plurality of memory cells to a format that supports arithmetic operations to a particular level of precision.

## Claims

### Claim 1

An apparatus, comprising:
a memory device; and
an analog to digital converter coupled to the memory device, wherein the analog to digital converter is configured to convert a bit string in an analog format to a posit format that supports arithmetic operations to a particular level of precision.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the memory device comprises a plurality of memory cells.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the plurality of memory cells are each configured to store data comprising a bit string.

### Claim 4 (depends on 2)

The apparatus of claim 2, wherein the plurality of memory cells are each configured to store data in the analog format.

### Claim 5 (depends on 1)

The apparatus of claim 1, further comprising a processing device coupled to a memory device.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the processing device is configured to cause data having the bit string with the posit format that supports arithmetic operations to be transferred to circuitry external to a host.

### Claim 7 (depends on 1)

The apparatus of claim 1, further comprising a controller, wherein the controller is coupled to the memory device and configured to send data comprising the bit string converted to the posit format that supports arithmetic operations to an external circuitry.

### Claim 8 (depends on 1)

The apparatus of claim 1, further comprising a digital to analog converter, wherein the digital to analog converter is configured to convert a received value in the posit format that supports arithmetic operations to the analog format.

### Claim 9

A method, comprising:
receiving, at a memory device, data comprising a bit string in a posit format that supports arithmetic operations to a particular level of precision; and
converting, via a digital to analog converter, the data to an analog format.

### Claim 10 (depends on 9)

The method of claim 9, comprising writing the data in the analog format in a memory cell of the memory device.

### Claim 11 (depends on 9)

The method of claim 9, comprising performing an operation using data written to a memory cell of the memory device resulting in additional data in the analog format.

### Claim 12 (depends on 11)

The method of claim 11, further comprising converting the additional data in the analog format to additional data in the posit format.

### Claim 13 (depends on 11)

The method of claim 11, further comprising sending the additional data in the posit format to a device external to the memory device.

### Claim 14 (depends on 11)

The method of claim 11, wherein performance of the operation on the data in the analog format occurs in a shorter amount of time or in a fewer number of sub-operations than when the operation is performed on the same data represented in the posit format.

### Claim 15 (depends on 9)

The method of claim 9, further comprising adding an analog weight to the data in the analog format resulting in adjusted data.

### Claim 16

A system, comprising:
a memory device, comprising:
control circuitry; and
a memory array coupled to the control circuitry; and
a digital to analog converter coupled to the memory device, wherein the digital to analog converter is configured to:
convert data comprising a bit string received in a posit format that supports arithmetic operations to a particular level of precision to an analog format; and
send the converted data to the control circuitry.

### Claim 17 (depends on 16)

The system of claim 16, wherein the memory array comprises a plurality of memory cells, wherein the plurality of memory cells are configured to store the data comprising the bit string in the analog format.

### Claim 18 (depends on 17)

The system of claim 17, further comprising an analog to digital converter coupled to the memory device and configured to convert data in the analog format to data in the posit format.

### Claim 19 (depends on 16)

The system of claim 16, wherein the control circuitry is configured to receive the data in the analog format.

### Claim 20 (depends on 19)

The system of claim 19, wherein the control circuitry is configured to cause performance of a neuromorphic operation on the data stored in the analog format.