# US 12,112,204 B2 · Modular accelerator function unit (AFU) design, discovery, and reuse

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- Number: US 12,112,204 B2
- Document ID: US12112204B2
- Status: Granted
- Kind: B2
- Application number: 17/884,244
- Filed: 2022-08-09
- Published: 2023-03-09
- Granted: 2024-10-08
- Earliest claimed: 2022-08-09
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Pratik M. Marolia; Aaron J. Grier; Henry M. Mitchel; Joseph Grecco; Michael C. Adler; Utkarsh Y. Kakaiya; Joshua D. Fender; Sundar Nadathur; Nagabhushan Chitlur
- Web page: https://patentgrep.com/patent/US12112204B2

## CPC

- G06F 9/5027: {the resource being a machine, e.g. CPUs, Servers, Terminals}
- G06F 9/468: {Specific access rights for resources, e.g. using capability register}
- G06F 9/4843: {by program, e.g. task dispatcher, supervisor, operating system}
- G06F 9/5044: {considering hardware capabilities}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A system comprising an accelerator circuit comprising an accelerator function unit to implement a first function, and one or more device feature header (DFH) circuits to provide attributes associated with the accelerator function unit, and a processor to retrieve the attributes of the accelerator function unit by traversing a device feature list (DFL) referencing the one or more DFH circuits, execute, based on the attributes, an application encoding the first function to cause the accelerator function unit to perform the first function.

## Claims

### Claim 1

An apparatus comprising:
function unit circuitry to implement at least a first function; and
one or more device feature header (DFH) registers to store attributes associated with the function unit circuitry,
wherein a DFH register is to at least store:
an identifier associated with the function unit circuitry,
a type description of the function unit circuitry,
an indication of a location of a next DFH register, and
a size of a corresponding memory-mapped input/output (MMIO) region.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein a type of the function unit circuitry is one or more of: accelerator function unit, basic building block, or private feature.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein a private feature is a feature within an accelerator function unit.

### Claim 4 (depends on 2)

The apparatus of claim 2, wherein a basic building block is a feature usable by a plurality of accelerator function units.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the function unit circuitry is to be programmed into a field programmable gate array (FPGA).

### Claim 6 (depends on 1)

The apparatus of claim 1, further comprising a processor core coupled to the function unit circuitry and one or more DFH registers.